Niklas Bruns

Orcid: 0000-0001-8921-4301

According to our database1, Niklas Bruns authored at least 8 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2023
Virtual prototype centric verification for embedded system development.
PhD thesis, 2023

Processor Verification using Symbolic Execution: A RISC-V Case-Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification.
Proceedings of the Forum on Specification & Design Languages, 2022

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Toward RISC-V CSR Compliance Testing.
IEEE Embed. Syst. Lett., 2021

2020
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019


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