Vladimir Herdt

IEEE Internet Things J., June, 2023

Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT.

[BibT_eX]

[DOI]

Dataset, January, 2023

Coverage-Guided Fuzzing for Plan-Based Robotics.

[BibT_eX]

[DOI]

Tim Meywerk

Proceedings of the 15th International Conference on Agents and Artificial Intelligence, 2023

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the Forum on Specification & Design Languages, 2023

Processor Verification using Symbolic Execution: A RISC-V Case-Study.

[BibT_eX]

[DOI]

Niklas Bruns

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.

[BibT_eX]

[DOI]

Dataset, July, 2022

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research.

[BibT_eX]

[DOI]

Sallar Ahmadi-Pour

J. Syst. Archit., 2022

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2022

Simulation-Based Debugging of Formal Environment Models.

[BibT_eX]

[DOI]

Proceedings of the 30th Mediterranean Conference on Control and Automation, 2022

Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype.

[BibT_eX]

[DOI]

Pascal Pieper

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

3D Visualization of Symbolic Execution Traces.

[BibT_eX]

[DOI]

Proceedings of the Forum on Specification & Design Languages, 2022

Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device.

[BibT_eX]

[DOI]

Proceedings of the Forum on Specification & Design Languages, 2022

Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification.

[BibT_eX]

[DOI]

Niklas Bruns

Proceedings of the Forum on Specification & Design Languages, 2022

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study.

[BibT_eX]

[DOI]

Klaus D. McDonald-Maier

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions.

[BibT_eX]

[DOI]

Milan Funck

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

The Scale4Edge RISC-V Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Verifying SystemC TLM peripherals using modern C++ symbolic execution tools.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2022

Automated Detection of Spatial Memory Safety Violations for Constrained Devices.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.

[BibT_eX]

[DOI]

Dataset, September, 2021

Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform.

[BibT_eX]

[DOI]

J. Syst. Archit., 2021

Toward RISC-V CSR Compliance Testing.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2021

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion.

[BibT_eX]

[DOI]

Sallar Ahmadi-Pour

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes.

[BibT_eX]

[DOI]

Proceedings of the 24th Forum on specification & Design Languages, 2021

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems.

[BibT_eX]

[DOI]

Sallar Ahmadi-Pour

Proceedings of the 24th Forum on specification & Design Languages, 2021

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Mutation-based Compliance Testing for RISC-V.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Verbessertes Virtual Prototyping für den Entwurfsablauf.

[BibT_eX]

[DOI]

Proceedings of the Ausgezeichnete Informatikdissertationen 2020., 2020

RISC-V based virtual prototype: An extensible and configurable platform for the system-level.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling.

[BibT_eX]

[DOI]

Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Applications, 2020

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study.

[BibT_eX]

[DOI]

Proceedings of the Forum for Specification and Design Languages, 2020

Towards Specification and Testing of RISC-V ISA Compliance⋆.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2020

2019

Efficient modeling, verification and analysis techniques to enhance the virtual prototype based design flow for embedded systems.

[BibT_eX]

[DOI]

PhD thesis, 2019

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2019

Systematic RISC-V based Firmware Design⋆.

[BibT_eX]

[DOI]

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Verifying Instruction Set Simulators using Coverage-guided Fuzzing*.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Maximizing power state cross coverage in firmware-based power management.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Towards Automated Refinement of TLM Properties to RTL.

[BibT_eX]

[DOI]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018

Extensible and Configurable RISC-V Based Virtual Prototype.

[BibT_eX]

[DOI]

Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Resilience evaluation via symbolic fault injection on intermediate code.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards fully automated TLM-to-RTL property refinement.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Early SoC security validation by VP-based static information flow analysis.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach.

[BibT_eX]

[DOI]

Proceedings of the 2017 Forum on Specification and Design Languages, 2017

Data flow testing for virtual prototypes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Compiled symbolic simulation for systemC.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Towards formal verification of real-world SystemC TLM peripheral models - a case study.

[BibT_eX]

[DOI]

Hoang Minh Le