Niklas Lotze

According to our database1, Niklas Lotze authored at least 12 papers between 2007 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2012
A Novel Hybrid Monotonic Local Search Algorithm for FIR Filter Coefficients Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 62 mV 0.13 µ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic.
IEEE J. Solid State Circuits, 2012

2011
Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma-Delta ADCs in Digital FM Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A multiplierless structure for direct digital IF signal synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Timing modeling for digital sub-threshold circuits.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
Variability of flip-flop timing at sub-threshold voltages.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Frame Based Memory Access Interpolation for A Digital Communication Modulator.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Study on self-timed asynchronous subthreshold logic.
Proceedings of the 25th International Conference on Computer Design, 2007


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