Niraj Nandan

According to our database1, Niraj Nandan authored at least 15 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Efficient in-cabin monitoring solution using TI TDA2PxSOCs.
Proceedings of the Autonomous Vehicles and Machines 2022, online, January 15-26, 2022, 2022

2021
DRAM Bandwidth Optimal Perspective Transform Engine.
Proceedings of the Autonomous Vehicles and Machines 2021, online, January 11-28, 2021, 2021

2020
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017
A 216 GOPS flexible WDR Image Processor for ADAS SoC.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2016
Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
Flexible Wide Dynamic Range (WDR) processing support in image signal processor (ISP).
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Accelerating H.264/HEVC video slice processing using application specific instruction set processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Image signal processing for front camera based automated driver assistance system.
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015

2014
Customization of de-blocking filter edge order for high performance: Study of H.264 AVC/SVC, H.265.
Proceedings of the 2014 IEEE International Symposium on Signal Processing and Information Technology, 2014

A 28nm programmable and low power ultra-HD video codec engine.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High performance DMA controller for ultra HDTV video codecs.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

A monolithic programmable Ultra-HD video codec engine.
Proceedings of the IEEE International Conference on Acoustics, 2014

High performance and flexible imaging Sub-system.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Efficient system level cache architecture for multimedia SoC.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

2013
High throughput VLSI architecture supporting HEVC loop filter for Ultra HDTV.
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013


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