Hetul Sanghvi

According to our database1, Hetul Sanghvi authored at least 15 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Novel Census Transform Hardware IP.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks.
Proceedings of the Computer Vision - ECCV 2020, 2020

2017
A 216 GOPS flexible WDR Image Processor for ADAS SoC.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2016
Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2015
Flexible Wide Dynamic Range (WDR) processing support in image signal processor (ISP).
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Accelerating H.264/HEVC video slice processing using application specific instruction set processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Image signal processing for front camera based automated driver assistance system.
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015

2014
Customization of de-blocking filter edge order for high performance: Study of H.264 AVC/SVC, H.265.
Proceedings of the 2014 IEEE International Symposium on Signal Processing and Information Technology, 2014

A 28nm programmable and low power ultra-HD video codec engine.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2D cache architecture for motion compensation in a 4K Ultra-HD AVC and HEVC video codec system.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

A monolithic programmable Ultra-HD video codec engine.
Proceedings of the IEEE International Conference on Acoustics, 2014

High performance and flexible imaging Sub-system.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Efficient system level cache architecture for multimedia SoC.
Proceedings of the 2014 International Conference on Advances in Computing, 2014


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