According to our database1, Niranjan Kulkarni authored at least 13 papers between 2009 and 2017.
Legend:Book In proceedings Article PhD thesis Other
Proceedings of the 54th Annual Design Automation Conference, 2017
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Enhanced Edge Adaptive Steganography Approach Using Threshold Value for Region Selection.
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Fast and robust differential flipflops and their extension to multi-input threshold gates.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture.
J. Parallel Distributed Comput., 2014
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the Formal Concept Analysis, 7th International Conference, 2009