Jae-sun Seo

According to our database1, Jae-sun Seo authored at least 100 papers between 2007 and 2020.

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Bibliography

2020
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Performance Modeling for CNN Inference Accelerators on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks.
IEEE J. Solid State Circuits, 2020

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism.
IEEE J. Solid State Circuits, 2020

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Benchmarking TinyML Systems: Challenges and Direction.
CoRR, 2020

Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Online Knowledge Acquisition with the Selective Inherited Model.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Efficient and Modularized Training on FPGA for Real-time Applications.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Noise-based Selection of Robust Inherited Model for Accurate Continual Learning.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019

A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019

Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2).
ACM J. Emerg. Technol. Comput. Syst., 2019

Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning.
ACM J. Emerg. Technol. Comput. Syst., 2019

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019

FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning.
CoRR, 2019

Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning.
Proceedings of Machine Learning and Systems 2019, 2019

Inference engine benchmarking across technological platforms from CMOS to RRAM.
Proceedings of the International Symposium on Memory Systems, 2019

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019

XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware.
J. Signal Process. Syst., 2018

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Process Scalability of Pulse-Based Circuits for Analog Image Convolution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.
ACM J. Emerg. Technol. Comput. Syst., 2018

Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning.
ACM J. Emerg. Technol. Comput. Syst., 2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr., 2018

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain.
CoRR, 2018

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Towards a Wearable Cough Detector Based on Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Low Power and Trusted Machine Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities.
IEEE J. Solid State Circuits, 2017

Improving efficiency in sparse learning with the feedforward inhibitory motif.
Neurocomputing, 2017

Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs.
Proceedings of the Advances in Computational Intelligence, 2017

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

End-to-end scalable FPGA accelerator for deep residual networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Designing ECG-based physical unclonable function for security of wearable devices.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Low-power neuromorphic speech recognition engine with coarse-grain sparsity.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering.
IEEE J. Solid State Circuits, 2016

Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.
CoRR, 2016

Reducing the Model Order of Deep Neural Networks Using Information Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

High-performance face detection with CPU-FPGA acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Bi-Level Rare Temporal Pattern Detection.
Proceedings of the IEEE 16th International Conference on Data Mining, 2016

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Ranking the parameters of deep neural networks using the fisher information.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.
Proceedings of the Symposium on VLSI Circuits, 2015

Digital CMOS neuromorphic processor design featuring unsupervised online learning.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Analysis and optimization of CMOS switched-capacitor converters.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

2013
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC.
IEEE J. Solid State Circuits, 2009

2008
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A robust alternate repeater technique for high performance busses in the multi-core era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the decreasing significance of large standard cells in technology mapping.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Robust ultra-low voltage ROM design.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Self-Time Regenerators for High-Speed and Low-Power Interconnect.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007


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