Shimeng Yu
Orcid: 0000-0002-0068-3652
According to our database1,
Shimeng Yu
authored at least 181 papers
between 2012 and 2024.
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Bibliography
2024
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
Computer, April, 2024
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS).
IEEE Trans. Emerg. Top. Comput., 2024
Towards Reverse-Engineering the Brain: Brain-Derived Neuromorphic Computing Approach with Photonic, Electronic, and Ionic Dynamicity in 3D integrated circuits.
CoRR, 2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024
2023
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
ACM Trans. Design Autom. Electr. Syst., 2023
Proxima: Near-storage Acceleration for Graph-based Approximate Nearest Neighbor Search in 3D NAND.
CoRR, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
An In-Storage Processing Architecture with 3D NAND Heterogeneous Integration for Spectra Open Modification Search.
Proceedings of the International Symposium on Memory Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash.
Proceedings of the IEEE International Memory Workshop, 2023
CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators.
Proceedings of the International Joint Conference on Neural Networks, 2023
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst., 2022
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers, 2022
IEEE Micro, 2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
IEEE Des. Test, 2022
Adv. Intell. Syst., 2022
Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators.
Proceedings of the IEEE International Memory Workshop, 2022
In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing.
Proceedings of the IEEE International Memory Workshop, 2022
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the Device Research Conference, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst., 2021
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Computers, 2021
A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture.
Robotics Auton. Syst., 2021
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits, 2021
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell., 2021
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications.
Proceedings of the Device Research Conference, 2021
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses.
IEEE Trans. Computers, 2020
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers, 2020
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020
IEEE Des. Test, 2020
SMART Paths for Latency Reduction in ReRAM Processing-In-Memory Architecture for CNN Inference.
CoRR, 2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 2020 Device Research Conference, 2020
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019
Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
MAX<sup>2</sup>: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
IEEE Des. Test, 2019
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Proceedings of the International Symposium on Memory Systems, 2019
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
Proceedings of the International Symposium on Memory Systems, 2019
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10<sup>-6</sup> Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations.
Proceedings of the International Conference on Neuromorphic Systems, 2019
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst., 2018
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
CoRR, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Reliability perspective of resistive synaptic devices on the neuromorphic system performance.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Neurocomputing, 2017
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, ISBN: 978-3-031-02030-8, 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Multi Scale Comput. Syst., 2016
J. Comput. Sci. Technol., 2016
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
ACM Trans. Design Autom. Electr. Syst., 2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.
CoRR, 2015
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Overview of resistive switching memory (RRAM) switching mechanism and device modeling.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2012