Shimeng Yu

According to our database1, Shimeng Yu authored at least 77 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System.
IEEE Trans. VLSI Syst., 2019

Three-Dimensional nand Flash for Vector-Matrix Multiplication.
IEEE Trans. VLSI Syst., 2019

Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

MAX2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area Utilization.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures.
IEEE Design & Test, 2019

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019

Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations.
Proceedings of the International Conference on Neuromorphic Systems, 2019

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System.
IEEE Trans. VLSI Syst., 2018

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. on Circuits and Systems, 2018

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Neuro-Inspired Computing With Emerging Nonvolatile Memorys.
Proceedings of the IEEE, 2018

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain.
CoRR, 2018

Special session on reliability and vulnerability of neuromorphic computing systems.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A Versatile ReRAM-based Accelerator for Convolutional Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Reliability perspective of resistive synaptic devices on the neuromorphic system performance.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Benchmark of RRAM based Architectures for Dot-Product Computation.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems.
IEEE Trans. VLSI Syst., 2017

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. VLSI Syst., 2017

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. VLSI Syst., 2017

Energy-Efficient Adaptive Computing With Multifunctional Memory.
IEEE Trans. on Circuits and Systems, 2017

Improving efficiency in sparse learning with the feedforward inhibitory motif.
Neurocomputing, 2017

Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Resistive Random Access Memory (RRAM)
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, 2016

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.
IEEE Trans. VLSI Syst., 2016

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning.
IEEE Trans. Multi-Scale Computing Systems, 2016

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol., 2016

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Design of a reliable RRAM-based PUF for compact hardware security primitives.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MNSIM: Simulation platform for memristor-based neuromorphic computing system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst., 2015

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.
CoRR, 2015

Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RRAM based synaptic devices for neuromorphic visual systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Overcoming the challenges of crossbar resistive memory architectures.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Exploiting resistive cross-point array for compact design of physical unclonable function.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On-chip Sparse Learning with Resistive Cross-point Array Architecture.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Design considerations of synaptic device for neuromorphic computing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design guidelines for 3D RRAM cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Overview of resistive switching memory (RRAM) switching mechanism and device modeling.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Architecting 3D vertical resistive memory for next-generation storage systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reliability-aware cross-point resistive memory design.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2012
Metal-Oxide RRAM.
Proceedings of the IEEE, 2012


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