Nisha Jacob

Orcid: 0000-0002-5603-6243

According to our database1, Nisha Jacob authored at least 11 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC.
J. Cryptogr. Eng., 2022

2021
SCA secure and updatable crypto engines for FPGA SoC bitstream decryption: extended version.
J. Cryptogr. Eng., 2021

2020
Secure Update of FPGA-based Secure Elements using Partial Reconfiguration.
IACR Cryptol. ePrint Arch., 2020

2019
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2017
How to Break Secure Boot on FPGA SoCs through Malicious Hardware.
IACR Cryptol. ePrint Arch., 2017

Securing FPGA SoC configurations independent of their manufacturers.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Compromising FPGA SoCs using malicious hardware blocks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014
Hardware Trojans: current challenges and approaches.
IET Comput. Digit. Tech., 2014

2012
Feasibility and Practicability of Standardized Cryptography on 4-bit Micro Controllers.
Proceedings of the Selected Areas in Cryptography, 19th International Conference, 2012

Standardized Signature Algorithms on Ultra-constrained 4-Bit MCU.
Proceedings of the Advances in Information and Computer Security, 2012


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