Neil Hanley
Orcid: 0000-0002-2595-7648
According to our database1,
Neil Hanley
authored at least 36 papers
between 2009 and 2022.
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Bibliography
2022
Proceedings of the 19th International Conference on Security and Cryptography, 2022
Proceedings of the E-Business and Telecommunications - 19th International Conference, 2022
2021
A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.
IEEE Trans. Emerg. Top. Comput., 2021
SCA secure and updatable crypto engines for FPGA SoC bitstream decryption: extended version.
J. Cryptogr. Eng., 2021
A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.
J. Cryptogr. Eng., 2021
2020
Plaintext: A Missing Feature for Enhancing the Power of Deep Learning in Side-Channel Analysis? Breaking multiple layers of side-channel countermeasures.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
2019
IEEE Trans. Computers, 2019
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
2018
Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
ACM Trans. Reconfigurable Technol. Syst., 2017
IEEE Trans. Computers, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.
IEEE Trans. Computers, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
2015
An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -.
Proceedings of the Information Security Applications - 16th International Workshop, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Exploiting Collisions in Addition Chain-Based Exponentiation Algorithms Using a Single Trace.
Proceedings of the Topics in Cryptology, 2015
2014
Proceedings of the 2014 IEEE International Workshop on Information Forensics and Security, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the Financial Cryptography and Data Security, 2014
2013
Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction.
IACR Cryptol. ePrint Arch., 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Proceedings of the Financial Cryptography and Data Security, 2013
2012
IACR Cryptol. ePrint Arch., 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2011
Int. J. Inf. Sec., 2011
2010
Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software.
Proceedings of the Trusted Systems - Second International Conference, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2009
FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, Lane, Shabal and Spectral Hash.
IACR Cryptol. ePrint Arch., 2009
Proceedings of the Information Security Applications, 10th International Workshop, 2009