Georg Sigl

According to our database1, Georg Sigl authored at least 118 papers between 1988 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
Other 

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Bibliography

2020
Machine learning and structural characteristics for reverse engineering.
Integr., 2020

RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography.
IACR Cryptol. ePrint Arch., 2020

Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage.
CoRR, 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020

Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Timing Resilience for Efficient and Secure Circuits.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A Calibratable Detector for Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Secure Physical Enclosures from Covers with Tamper-Resistance.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks.
CoRR, 2019

Network Scanning and Mapping for IIoT Edge Node Device Security.
CoRR, 2019

A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices.
CoRR, 2019

Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices.
CoRR, 2019

Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Improving on State Register Identification in Sequential Hardware Reverse Engineering.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field.
Proceedings of the 2019 International Conference on Embedded Wireless Systems and Networks, 2019

Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction.
IACR Cryptol. ePrint Arch., 2018

18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices.
IACR Cryptol. ePrint Arch., 2018

DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries.
Proceedings of the 27th USENIX Security Symposium, 2018

Experimental Power and Performance Evaluation of CAESAR Hardware Finalists.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Dividing the threshold: Multi-probe localized EM analysis on threshold implementations.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Towards the formal verification of security properties of a Network-on-Chip router.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A measurement system for capacitive PUF-based security enclosures.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs.
Microprocess. Microsystems, 2017

Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection.
Microprocess. Microsystems, 2017

Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier.
Microprocess. Microsystems, 2017

Fast and reliable PUF response evaluation from unsettled bistable rings.
Microprocess. Microsystems, 2017

How to Break Secure Boot on FPGA SoCs through Malicious Hardware.
IACR Cryptol. ePrint Arch., 2017

Pushing the Limits Further: Sub-Atomic AES.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Securing FPGA SoC configurations independent of their manufacturers.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A security-aware routing implementation for dynamic data protection in zone-based MPSoC.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Towards Protected MPSoC Communication for Information Protection against a Malicious NoC.
Proceedings of the International Conference on Computational Science, 2017

Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Take a moment and have some t: Hypothesis testing on raw PUF data.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Compromising FPGA SoCs using malicious hardware blocks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Towards post-quantum security for IoT endpoints with NTRU.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

2016
Cherry-Picking Reliable PUF Bits With Differential Sequence Coding.
IEEE Trans. Information Forensics and Security, 2016

Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs.
Journal of Circuits, Systems, and Computers, 2016

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions.
IACR Cryptol. ePrint Arch., 2016

A flexible framework for mobile device forensics based on cold boot attacks.
EURASIP J. Inf. Secur., 2016

Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A security aware routing approach for NoC-based MPSoCs.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Towards risk aware NoCs for data protection in MPSoCs.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

MaskVer: a tool helping designers detect flawed masking implementations.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

An area-optimized serial implementation of ICEPOLE authenticated encryption schemes.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016

Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach.
Proceedings of the Foundations and Practice of Security - 9th International Symposium, 2016

Attack on a DFA Protected AES by Simultaneous Laser Fault Injections.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

Towards Efficient Evaluation of a Time-Driven Cache Attack on Modern Processors.
Proceedings of the Computer Security - ESORICS 2016, 2016

X25519 Hardware Implementation for Low-Latency Applications.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Practical evaluation of code injection in encrypted firmware updates.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Hiding Higher-Order Univariate Leakages by Shuffling Polynomial Masking Schemes: A More Efficient, Shuffled, and Higher-Order Masked AES S-box.
Proceedings of the ACM Workshop on Theory of Implementation Security, 2016

Online Reliability Testing for PUF Key Derivation.
Proceedings of the 6th International Workshop on Trustworthy Embedded Devices, 2016

Automated Detection of Instruction Cache Leaks in Modular Exponentiation Software.
Proceedings of the Smart Card Research and Advanced Applications, 2016

Squeezing Polynomial Masking in Tower Fields - A Higher-Order Masked AES S-Box.
Proceedings of the Smart Card Research and Advanced Applications, 2016

2015
Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs.
Microprocess. Microsystems, 2015

Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions.
Datenschutz und Datensicherheit, 2015

On Error Correction for Physical Unclonable Functions.
CoRR, 2015

Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Aging effects on ring-oscillator-based physical unclonable functions on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Petite and Power Saving Design for the AES S-Box.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Improving Non-profiled Attacks on Exponentiations Based on Clustering and Extracting Leakage from Multi-channel High-Resolution EM Measurements.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015

Side Channel Attacks on Smartphones and Embedded Devices Using Standard Radio Equipment.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015

Precise Laser Fault Injections into 90 nm and 45 nm SRAM-cells.
Proceedings of the Smart Card Research and Advanced Applications, 2015

seTPM: Towards Flexible Trusted Computing on Mobile Devices Based on GlobalPlatform Secure Elements.
Proceedings of the Smart Card Research and Advanced Applications, 2015

A Lightweight Framework for Cold Boot Based Forensics on Mobile Devices.
Proceedings of the 10th International Conference on Availability, Reliability and Security, 2015

2014
Hardware Trojans: current challenges and approaches.
IET Computers & Digital Techniques, 2014

Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes.
CoRR, 2014

A Low Area Probing Detector for Power Efficient Security ICs.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014

Ciphertext-Only Fault Attacks on PRESENT.
Proceedings of the Lightweight Cryptography for Security and Privacy, 2014

Investigating measurement methods for high-resolution electromagnetic field side-channel analysis.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Reconfigurable PUFs for FPGA-based SoCs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

On Cache Timing Attacks Considering Multi-core Aspects in Virtualized Embedded Systems.
Proceedings of the Trusted Systems - 6th International Conference, 2014

On MILS I/O Sharing Targeting Avionic Systems.
Proceedings of the 2014 Tenth European Dependable Computing Conference, 2014

Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Increasing the efficiency of syndrome coding for PUFs with helper data compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Risk management in embedded devices using metering applications as example.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013
Protecting PUF Error Correction by Codeword Masking.
IACR Cryptol. ePrint Arch., 2013

Clustering Algorithms for Non-Profiled Single-Execution Attacks on Exponentiations.
IACR Cryptol. ePrint Arch., 2013

A new model for estimating bit error probabilities of Ring-Oscillator PUFs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Differential scan-path: A novel solution for secure design-for-testability.
Proceedings of the 2013 IEEE International Test Conference, 2013

On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective.
Proceedings of the Progress in Cryptology - INDOCRYPT 2013, 2013

Localized electromagnetic analysis of RO PUFs.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Comprehensive analysis of software countermeasures against fault attacks.
Proceedings of the Design, Automation and Test in Europe, 2013

Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes.
Proceedings of the TrustED'13, 2013

Identities for Embedded Systems Enabled by Physical Unclonable Functions.
Proceedings of the Number Theory and Cryptography, 2013

2012
Physical Unclonable Functions.
Datenschutz und Datensicherheit, 2012

Detection of probing attempts in secure ICs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Complementary IBS: Application specific error correction for PUFs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Localized Electromagnetic Analysis of Cryptographic Implementations.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

Strengths and Limitations of High-Resolution Electromagnetic Field Measurements for Side-Channel Analysis.
Proceedings of the Smart Card Research and Advanced Applications, 2012

Reliability bound and channel capacity of IBS-based fuzzy embedders.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Side-Channel Analysis of PUFs and Fuzzy Extractors.
Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011

Keynote address: Design of secure systems - Where are the EDA tools?
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A Cost-Effective FPGA-based Fault Simulation Environment.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

1992
Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung.
PhD thesis, 1992

Accurate net models for placement improvement by network flow methods.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Parallel algorithms for slicing based final placement.
Proceedings of the conference on European design automation, 1992

1991
GORDIAN: VLSI placement by quadratic programming and slicing optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities.
Proceedings of the VLSI 91, 1991

A New Linear Placement Algorithm for Cell Generation.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Goal oriented slicing enumeration through shape function clipping.
Proceedings of the conference on European design automation, 1991

Analytical Placement: A Linear or a Quadratic Objective Function?
Proceedings of the 28th Design Automation Conference, 1991

1988
GORDIAN: a new global optimization/rectangle dissection method for cell placement.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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