Michael Pehl

Niranjana Papagudi Subrahmanyam

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024

2023

A Practical Approach to Estimate the Min-Entropy in PUFs.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., December, 2023

Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations.

[BibT_eX]

[DOI]

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses.

[BibT_eX]

[DOI]

Seyed Hamidreza Moghadas

IEEE Trans. Very Large Scale Integr. Syst., 2022

When the Decoder Has to Look Twice: Glitching a PUF Error Correction.

[BibT_eX]

[DOI]

Jonas Ruchti

Michael Gruber

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Interleaved Challenge Loop PUF: A Highly Side-Channel Protected Oscillator-Based PUF.

[BibT_eX]

[DOI]

Jean-Luc Danger

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Towards More Secure PUF Applications: A Low-Area Polar Decoder Implementation.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Beware of the Bias - Statistical Performance Evaluation of Higher-Order Alphabet PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

On-Chip Side-Channel Analysis of the Loop PUF.

[BibT_eX]

[DOI]

Moritz Wettermann

Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022

2021

Machine Learning of Physical Unclonable Functions using Helper Data Revealing a Pitfall in the Fuzzy Commitment Scheme.

[BibT_eX]

[DOI]

Emanuele Strieder

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Analysis and Protection of the Two-metric Helper Data Scheme.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Testing and Reliability Enhancement of Security Primitives.

[BibT_eX]

[DOI]

Md Toufiq Hasan Anik

Jean-Luc Danger

Omar Diankha

Mohammad Ebrahimabadi

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Secure Update of FPGA-based Secure Elements using Partial Reconfiguration.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Self-Secured PUF: Protecting the Loop PUF by Masking.

[BibT_eX]

[DOI]

Jean-Luc Danger

IACR Cryptol. ePrint Arch., 2020

PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT Devices.

[BibT_eX]

[DOI]

Michael Tempelmeier

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Spatial Context Tree Weighting for Physical Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2020

ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt Detector.

[BibT_eX]

[DOI]

Seyed Hamidreza Moghadas

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Towards memory integrity and authenticity of multi-processors system-on-chip using physical unclonable functions.

[BibT_eX]

[DOI]

Johanna Sepúlveda

Felix Wilgerodt

it Inf. Technol., 2019

Side-Channel Analysis of the TERO PUF.

[BibT_eX]

[DOI]

Vincent Immler

IACR Cryptol. ePrint Arch., 2019

Efficient Bound for Conditional Min-Entropy of Physical Unclonable Functions Beyond IID.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Information Forensics and Security, 2019

On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

Spatial Correlation Analysis on Physical Unclonable Functions.

[BibT_eX]

[DOI]

Berndt M. Gammel

IEEE Trans. Inf. Forensics Secur., 2018

Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

SEPUFSoC: Using PUFs for Memory Integrity and Authentication in Multi-Processors System-on-Chip.

[BibT_eX]

[DOI]

Johanna Sepúlveda

Felix Wilgerodt

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips.

[BibT_eX]

[DOI]

Mathieu Gross

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

Securing FPGA SoC configurations independent of their manufacturers.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation.

[BibT_eX]

[DOI]

Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, 2017

2016

Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures.

[BibT_eX]

[DOI]

Helmut Graeb

J. Circuits Syst. Comput., 2016

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

2015

Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions.

[BibT_eX]

[DOI]

Datenschutz und Datensicherheit, 2015

Systematic Low Leakage Coding for Physical Unclonable Functions.

[BibT_eX]

[DOI]

Meng-Day (Mandel) Yu

Proceedings of the 10th ACM Symposium on Information, 2015

2014

Herausforderungen der ganzheitlichen Absicherung eingebetteter Systeme.

[BibT_eX]

[DOI]

Hermann Seuschek

Datenschutz und Datensicherheit, 2014

Statistic-based security analysis of ring oscillator PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Advanced performance metrics for Physical Unclonable Functions.

[BibT_eX]

[DOI]

Akshara Ranjit Punnakkal

Helmut Graeb

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

A new model for estimating bit error probabilities of Ring-Oscillator PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

2012

Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach.

[BibT_eX]

[DOI]

Helmut E. Graeb

J. Circuits Syst. Comput., 2012

2010

Sizing analog circuits using an SQP and Branch and Bound based approach.

[BibT_eX]

[DOI]