Nishith N. Chakraborty

Orcid: 0009-0003-0287-0042

According to our database1, Nishith N. Chakraborty authored at least 11 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Efficient and Accurate Memristive Memory for Array-Based Spiking Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Optimizations for a Current-Controlled Memristor- Based Neuromorphic Synapse Design.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks.
CoRR, 2023

Energy Efficient and High-Performance Synaptic Operating Point Evaluation for SNN Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Homeostatic Plasticity in a Leaky Integrate and Fire Neuron Using Tunable Leak.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Spike-Driven Synaptic Plasticity for a Memristive Neuromorphic Core.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Spike-Timing-Dependent Plasticity for a Hafnium-Oxide Memristive Synapse.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
STDP Based Online Learning for a Current-Controlled Memristive Synapse.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Programmable Refractory Period Implementations in a Mixed-Signal Integrate-And-Fire Neuron.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021


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