Nobuya Watanabe

According to our database, Nobuya Watanabe authored at least 30 papers between 2004 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays.

Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

IEEE Access, 2026

Mono Instruction Set Computer design using a high-level hardware description language.

Nobuya Watanabe, Minoru Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

Flip-flop resource expansion method for FPGAs using latches created on look-up tables.

Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

OpenOCD-Compliant Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Array VLSIs.

Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

An implementation of a quantum algorithm on a Cyclone FPGA.

Haruto Kurokawa, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

Soft-error measurement for a radiation-hardened RISC-V processor.

Masato Isobe, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2026

2025

Triple Modular Redundancy Logic Design from High-Level Hardware Description.

Nobuya Watanabe, Minoru Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Realization of Wafer-Scale VLSI Using Optical Configuration Architecture.

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines.

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI.

Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA.

Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays.

Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Implementation of Mono Instruction Set Computer with Small Register Files.

Soma Imai, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2025

Reliability Calculation for Captured Images in Mobile Observation for Natural Environments.

Yukito Seo, Kosuke Takano, Nobuya Watanabe, Kin Fun Li

Proceedings of the Advances in Internet, Data and Web Technologies, 2025

Delay adjustment circuit for a triple modular redundant communication system used for radiation-hardened robots.

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 2025 8th International Conference on Computational Intelligence and Intelligent Systems, 2025

2024

Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI.

Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Application design system for high-speed dynamically reconfigurable gate arrays.

Nobuya Watanabe, Ryoya Ishitani, Minoru Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Wafer-scale VLSI realization using programmable architecture.

Atsushi Takata, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Remote monitoring system for optically reconfigurable gate arrays in radiation environments.

Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory.

Sae Goto, Minoru Watanabe, Akifumi Ogiwara, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI.

Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

A Classification Method of Image Feature Using Neural Metric Learning for Natural Environment Video.

Yukito Seo, Rafly Arief Kanza, Nobuya Watanabe, Kin Fun Li, Kosuke Takano

Proceedings of the Advanced Information Networking and Applications, 2024

2023

An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit.

Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Multi-context-scrubbing operation for a 1-bit counter circuit.

Kakeru Ando, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor.

Daisuke Bamba, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2023

Video Indexing for Live Nature Camera on Digital Earth.

Hiroki Mimura, Masaya Tahara, Kosuke Takano, Nobuya Watanabe, Kin Fun Li

Proceedings of the Advanced Information Networking and Applications, 2023

2022

Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI.

Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Convolutional neural network implementations using Vitis AI.

Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya

Proceedings of the 12th IEEE Annual Computing and Communication Workshop and Conference, 2022

Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration.

Sae Goto, Minoru Watanabe, Nobuya Watanabe

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2004

Characteristics of the multiple-input DC-DC converter.

Hirofumi Matsuo, Wenzhong Lin, Fujio Kurokawa, Tetsuro Shigemizu, Nobuya Watanabe

IEEE Trans. Ind. Electron., 2004