Minoru Watanabe

According to our database1, Minoru Watanabe authored at least 113 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
FPGA implementation of a robot control algorithm.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

2018
Foreword.
IEICE Transactions, 2018

High total-ionizing-dose tolerance field programmable gate array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

Advanced Devices and Architectures.
Proceedings of the Principles and Structures of FPGAs., 2018

2017
Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays.
Proceedings of the 15th IEEE Intl Conf on Dependable, 2017

500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays.
Proceedings of the 11th International Conference on Computer Science & Education, 2016

Full FPGA game machine.
Proceedings of the IEEE International Conference on Consumer Electronics, 2016

A 200 Mrad Radiation Tolerance of a Polymer-Dispersed Liquid Crystal Holographic Memory.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

Direct optical communication on an optically reconfigurable gate array.
Proceedings of the Fifth International Conference on Future Communication Technologies, 2016

2015
Sustainable advantage of a parallel configuration in an optical FPGA.
Proceedings of the 2015 IEEE/SICE International Symposium on System Integration, 2015

FPGA Trax Solver based on a neural network design.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Parallel-Operation-Oriented Optically Reconfigurable Gate Array.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Holographic scrubbing technique for a programmable gate array.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Radiation Tolerance of Color Configuration on an Optically Reconfigurable Gate Array.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Optically reconfigurable gate array with an angle-multiplexed holographic memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Dependability-increasing technique for a multi-context optically reconfigurable gate array.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

0.18 μm CMOS process photodiode memory.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

FPGA Blokus Duo Solver using a massively parallel architecture.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Color configuration method for an optically reconfigurable gate array.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Image recognition operation on a dynamically reconfigurable vison architecture.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Dependability-Increasing Method of Processors under a Space Radiation Environment.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI.
SIGARCH Computer Architecture News, 2012

Gray-level image recognition on a dynamically reconfigurable vision architecture.
Proceedings of the IEEE 25th International SOC Conference, 2012

A Uniform Partitioning Method for Mono-Instruction Set Computer (MISC).
Proceedings of the 15th International Conference on Network-Based Information Systems, 2012

0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control.
TRETS, 2011

A MEMS writer system embedded for a programmable optically reconfigurable gate array.
SIGARCH Computer Architecture News, 2011

A 144-configuration context MEMS optically reconfigurable gate array.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Triple module redundancy scheme on an optically reconfigure gate array.
Proceedings of the International SoC Design Conference, 2011

An FPGA Connect6 Solver with a two-stage pipelined evaluation.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A 100-context optically reconfigurable gate array.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 64-context MEMS optically reconfigurable gate array.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Othello Solver based on a soft-core MIMD processor array.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Dynamically Reconfigurable Vision-Chip Architecture.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Recovery method for a turn-off failure mode of a laser array on an ORGA.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Acceleration method of optical reconfigurations using analog configuration contexts.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Binary MEMS Optically Reconfigurable Gate Array.
Proceedings of the 9th IEEE/ACIS International Conference on Computer and Information Science, 2010

2009
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Fast Reconfiguration Experiments of an Optically Differential Reconfigurable Gate Array with Nine Configuration Contexts.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 13.75 ns Holographic Reconfiguration of an Optically Differential Reconfigurable Gate Array.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

A nine-context programmable optically reconfigurable gate array with semiconductor lasers.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Mems optically reconfigurable gate array.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Alignment compensation method for an optically reconfigurable gate array.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A Multi-Context Programmable Optically Reconfigurable Gate Array.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A 16-context Optically Reconfigurable Gate Array.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Fast Optical Reconfiguration of a Nine-Context DORGA.
Proceedings of the Reconfigurable Computing: Architectures, 2009

A Sixteen-Context Dynamic Optically Reconfigurable Gate Array.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
An Optical Reconfiguration System with Four Contexts.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

An Acceleration and Optimization Method for Optical Reconfiguration.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Analysis of retention time under multi-configuration on a DORGA.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Defect tolerance of holographic configurations in ORGAs.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

An 11, 424-gate dynamic optically reconfigurable gate array VLSI.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A 770ns Holographic Reconfiguration of a Four-Context DORGA.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Dynamic holographic reconfiguration on a four-context ODRGA.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Holographic memory reconfigurable VLSI.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

272 Gate Count Optically Differential Reconfigurable Gate Array VLSI.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
An optically differential reconfigurable gate array with a holographic memory.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Power consumption advantage of a dynamic optically reconfigurable gate array.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Differential Reconfiguration Architecture suitable for a Holographic Memory.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Logic Synthesis and Place-and-Route Environment for ORGAs.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Optically Reconfigurable Gate Arrays vs. ASICs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
An Improved Dynamic Optically Reconfigurable Gate Array.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004
An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An optically differential reconfigurable gate array using a 0.18 μm CMOS process.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.
Proceedings of the Field Programmable Logic and Application, 2004

Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Testing Method for Optical Connections Using Gate Array Structure in ORGAs.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
An FPGA Implementation of Finite Physical Quantity Neural Network.
JRM, 2003

An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
An optically differential reconfigurable gate array and its power consumption estimation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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