Omid Sarbishei

Orcid: 0000-0001-5677-2462

According to our database1, Omid Sarbishei authored at least 25 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Quantitative Comparison of Overlapping and Non-Overlapping Sliding Windows for Human Activity Recognition Using Inertial Sensors.
Sensors, 2019

Refined Lightweight Temporal Compression for Energy-Efficient Sensor Data Streaming.
Proceedings of the 5th IEEE World Forum on Internet of Things, 2019

A Platform and Methodology Enabling Real-Time Motion Pattern Recognition on Low-Power Smart Devices.
Proceedings of the 5th IEEE World Forum on Internet of Things, 2019

The Impact of Data Reduction on Wearable-Based Human Activity Recognition.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops, 2019

2018
A multi-dimensional extension of the Lightweight Temporal Compression method.
Proceedings of the IEEE International Conference on Big Data (IEEE BigData 2018), 2018

2016
On the accuracy improvement of low-power orientation filters using IMU and MARG sensor arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A minimum MSE sensor fusion algorithm with tolerance to multiple faults.
Proceedings of the 18th IEEE European Test Symposium, 2013

An efficient fault-tolerant sensor fusion algorithm for accelerometers.
Proceedings of the 2013 IEEE International Conference on Body Sensor Networks, 2013

2012
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT).
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

MSE minimization and fault-tolerant data fusion for multi-sensor systems.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Analysis of Mean-Square-Error (MSE) for fixed-point FFT units.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009
A Formal Approach for Debugging Arithmetic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

High-level optimization of integer multipliers over a finite bit-width with verification capabilities.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Polynomial datapath optimization using partitioning and compensation heuristics.
Proceedings of the 46th Design Automation Conference, 2009

2008
Arithmetic Circuits Verification without Looking for Internal Equivalences.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

2007
A high-performance architecture for irregular LDPC decoding algorithm using input-multiplexing method.
Proceedings of the 9th International Symposium on Signal Processing and Its Applications, 2007

Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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