Mahmoud Tabandeh

According to our database1, Mahmoud Tabandeh authored at least 25 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Employing Topical Relations in Semantic Analysis of Traffic Videos.
IEEE Intell. Syst., 2019

Cluster-based sparse topical coding for topic mining and document clustering.
Adv. Data Anal. Classif., 2018

A soft error tolerant register file for highly reliable microprocessor design.
Int. J. High Perform. Syst. Archit., 2017

Abnormal event detection and localisation in traffic videos based on group sparse topical coding.
IET Image Process., 2016

Temporal segmentation of traffic videos based on traffic phase discovery.
Proceedings of the 2016 IEEE/IFIP Network Operations and Management Symposium, 2016

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations.
J. Circuits Syst. Comput., 2015

Data Bits in Karnaugh Map and Increasing Map Capability in Error Correcting.
CoRR, 2015

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Modeling traffic motion patterns via Non-negative Matrix Factorization.
Proceedings of the 2015 IEEE International Conference on Signal and Image Processing Applications, 2015

Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients.
J. Circuits Syst. Comput., 2014

Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation.
Microelectron. Reliab., 2013

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits.
IEEE Des. Test, 2013

Multi-hop communications on wireless network-on-chip using optimized phased-array antennas.
Comput. Electr. Eng., 2013

Graph based fault model definition for bus testing.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Test data compression strategy while using hybrid-BIST methodology.
Proceedings of the East-West Design & Test Symposium, 2013

Functional fault model definition for bus testing.
Proceedings of the East-West Design & Test Symposium, 2013

Application of Karnaugh map for easy generation of error correcting codes.
Sci. Iran., 2012

Single event upset immune latch circuit design using C-element.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A novel pipeline architecture of replacing Ink Drop Spread.
Proceedings of the Second World Congress on Nature & Biologically Inspired Computing, 2010

A Formal Approach for Debugging Arithmetic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

High-level optimization of integer multipliers over a finite bit-width with verification capabilities.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

A Thermal-aware Shortest Hop Routing Algorithm for in vivo Biomedical Sensor Networks.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

A Fair Routing Algorithm for Wireless Mesh Networks Based on Game Theory.
Proceedings of the Eighth International Conference on Networks, 2009

Jitter-Buffer Management for VoIP over Wireless LAN in a Limited Resource Device.
Proceedings of the Fourth International Conference on Networking and Services, 2008

Compact and Secure Design of Masked AES S-Box.
Proceedings of the Information and Communications Security, 9th International Conference, 2007