Masahiro Fujita

According to our database1, Masahiro Fujita
  • authored at least 370 papers between 1983 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch.
IEEE Trans. VLSI Syst., 2017

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.
J. Solid-State Circuits, 2017

A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

On Testing of Superscalar Processors in Functional Mode for Delay Faults.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Slyware Prevention: Threat of Websites Inducing Accidental Taps and Countermeasures.
Proceedings of the Advances in Network-Based Information Systems, 2017

Testing multiple stuck-at faults of ROBDD based combinational circuit design.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Post-silicon observability enhancement with topology based trace signal selection.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Systematic approximate logic optimization using don't care conditions.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A new approach for selecting inputs of logic functions during debug.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A low-cost approximate 32-point transform architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A new approach for diagnosing bridging faults in logic designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Instruction-based self-test for delay faults maximizing operating temperature.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Distributed Particle-Based Rendering Framework for Large Data Visualization on HPC Environments.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

An approach to approximate computing: Logic transformations for one-minterm changes in specification.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

RTL level trace signal selection and coverage estimation during post-silicon validation.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Combining Restorability and Error Detection Ability for Effective Trace Signal Selection.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Dissemination of edge-heavy data on heterogeneous MQTT brokers.
Proceedings of the 6th IEEE International Conference on Cloud Networking, 2017

2016
Fast and Efficient Signature-Based Sub-Circuit Matching.
IEICE Transactions, 2016

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Two axes orthogonal drive transmission for omnidirectional crawler with surface contact.
Proceedings of the 2016 IEEE International Symposium on Safety, 2016

Variable inner volume mechanism for soft and robust gripping - Improvement of gripping performance for large-object gripping.
Proceedings of the 2016 IEEE International Symposium on Safety, 2016

Study on relationship between user awareness and QoE in communication delay on smartphones.
Proceedings of the 14th Annual Conference on Privacy, Security and Trust, 2016

Directcha: A proposal of spatiometric mental rotation CAPTCHA.
Proceedings of the 14th Annual Conference on Privacy, Security and Trust, 2016

A Micro Biometric Authentication Mechanism Considering Minute Patterns of the Human Body: A Proposal and the First Attempt.
Proceedings of the 19th International Conference on Network-Based Information Systems, 2016

Automatically adjusting system level designs after RTL/gate-level ECO.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Specification by existing design plus use-cases.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Secure Communication Protocol Between a Human and a Bank Server for Preventing Man-in-the-Browser Attacks.
Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2016

Implementation and Initial Evaluation of Game in Which Password Enhancement Factor is Embedded.
Proceedings of the HCI International 2016 - Posters' Extended Abstracts, 2016

Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns.
Proceedings of the Automated Technology for Verification and Analysis, 2016

A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formally analyzing fault tolerance in datapath designs using equivalence checking.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology.
IEEE Trans. VLSI Syst., 2015

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition.
IEEE Trans. Computers, 2015

Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design.
Proceedings of the IEEE, 2015

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register.
J. Solid-State Circuits, 2015

Direct simulation of drying colloidal suspension on substrate using immersed free surface model.
J. Comput. Physics, 2015

UPF-based formal verification of low power techniques in modern processors.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Efficient signature-based sub-circuit matching.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Delay Testing Based on Multiple Faulty Behaviors.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Analysis and testing on delays with two time frames.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Trace signal selection methods for post silicon debugging.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Physical trust-based persistent authentication.
Proceedings of the 13th Annual Conference on Privacy, Security and Trust, 2015

An Attempt to Memorize Strong Passwords while Playing Games.
Proceedings of the 18th International Conference on Network-Based Information Systems, 2015

Logic analysis and optimization with quick identification of invariants through one time frame analysis.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

Hardware in loop testing of an insulin pump.
Proceedings of the 2015 IEEE International Test Conference, 2015

16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Incremental ATPG methods for multiple faults under multiple fault models.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Automatic identification of assertions and invariants with small numbers of test vectors.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Chimera CAPTCHA: A Proposal of CAPTCHA Using Strangeness in Merged Objects.
Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2015

On Implementation of LUT with Large Numbers of Inputs (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Temperature-aware software-based self-testing for delay faults.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
In vitro and in vivo evaluation of 11C-SD5024, a novel PET radioligand for human brain imaging of cannabinoid CB1 receptors.
NeuroImage, 2014

Retest imaging of [11C]NOP-1A binding to nociceptin/orphanin FQ peptide (NOP) receptors in the brain of healthy humans.
NeuroImage, 2014

Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor.
IEEE Micro, 2014

SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.
IPSJ Trans. System LSI Design Methodology, 2014

An Energy-Efficient Patchable Accelerator and Its Design Methods.
IEICE Transactions, 2014

Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model.
IEICE Transactions, 2014

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.
Proceedings of the Symposium on VLSI Circuits, 2014

Logic synthesis and verification on fixed topology.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

i/k-Contact: A context-aware user authentication using physical social trust.
Proceedings of the 2014 Twelfth Annual International Conference on Privacy, 2014

Efficient SAT-based ATPG techniques for all multiple stuck-at faults.
Proceedings of the 2014 International Test Conference, 2014

Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Specification and formal verification of power gating in processors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

RTL datapath optimization using system-level transformations.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Multi-step image compositing for massively parallel rendering.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

An Image-Based CAPTCHA Using Sophisticated Mental Rotation.
Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2014

Improving polynomial datapath debugging with HEDs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2013
On the integration of model-driven design and dynamic assertion-based verification for embedded software.
Journal of Systems and Software, 2013

Special session 4B: Elevator talks.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Debugging Methods Through Identification of Appropriate Functions for Internal Gates.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

A debugging method for gate level circuit designs by introducing programmability.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

FOF: Functionally Observable Fault and its ATPG techniques.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Hardware implementation of BLTL property checkers for acceleration of statistical model checking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Partial synthesis through sampling with and without specification.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Debugging processors with advanced features by reprogramming LUTs on FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
Population-based input function and image-derived input function for [11C](R)-rolipram PET imaging: Methodology, validation and application to the study of major depressive disorder.
NeuroImage, 2012

Quantification of metabotropic glutamate subtype 5 receptors in the brain by an equilibrium method using 18F-SP203.
NeuroImage, 2012

Transaction Ordering in Network-on-Chips for Post-Silicon Validation.
IEICE Transactions, 2012

Time-Constraint-Aware Optimization of Assertions in Embedded Software.
J. Electronic Testing, 2012

Verifying Reliability (Dagstuhl Seminar 12341).
Dagstuhl Reports, 2012

An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

SEU Tolerant Robust Latch Design.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Distance aware ray tracing for curves.
Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2012

Future direction of digital content: 20th anniversary keynote talk.
Proceedings of the 20th ACM Multimedia Conference, MM '12, Nara, Japan, October 29, 2012

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Transaction-based post-silicon debug of many-core System-on-Chips.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

SEU tolerant robust memory cell design.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Automatic assertion extraction in gate-level simulation using GPGPUs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Post-silicon verification and debugging with control flow traces and patchable hardware.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

A functional test generation technique for RTL datapaths.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Automatic rectification of design errors in complex processors with programmable hardware.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Post-silicon debugging targeting electrical errors with patchable controllers (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Simulation-Based Analysis of Cyberphysical Systems.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Dynamic property mining for embedded software.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Automated data analysis techniques for a modern silicon debug environment.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

On error tolerance and Engineering Change with Partially Programmable Circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Post-silicon patching for verification/debugging with high-level models and programmable logic.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Kinetic analysis in human brain of [11C](R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function.
NeuroImage, 2011

Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability.
IPSJ Trans. System LSI Design Methodology, 2011

Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. System LSI Design Methodology, 2011

Multi-Level Bounded Model Checking with Symbolic Counterexamples.
IEICE Transactions, 2011

An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging.
IEICE Transactions, 2011

Tutorial: "Post silicon debug of SOC designs".
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

EFSM-based model-driven approach to concolic testing of system-level design.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

SEU tolerant SRAM cell.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Global transaction ordering in Network-on-Chips for post-silicon validation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Early case splitting and false path detection to improve high level ATPG techniques.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Automated System Testing of Dynamic Web Applications.
Proceedings of the Software and Data Technologies - 6th International Conference, 2011

Client-tier Validation of Dynamic Web Applications.
Proceedings of the ICSOFT 2011, 2011

Model-driven design and validation of embedded software.
Proceedings of the 6th International Workshop on Automation of Software Test, 2011

Formal verification guided automatic design error diagnosis and correction of complex processors.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Modular equivalence verification of polynomial datapaths with multiple word-length operands.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.
Proceedings of the 16th European Test Symposium, 2011

An energy-efficient patchable accelerator for post-silicon engineering changes.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols.
Proceedings of the Automated Technology for Verification and Analysis, 2011

High Level Verification and Its Use at Pos-Silicon Debugging and Patching.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

On-chip dynamic signal sequence slicing for efficient post-silicon debugging.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Utilizing high level design information to speed up post-silicon debugging.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Modular Datapath Optimization and Verification Based on Modular-HED.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Category: Methodology: Quantification and test-retest study of 11C-(R)-rolipram, a PET tracer of the cAMP cascade, using an arterial input function and an image-derived input function.
NeuroImage, 2010

Image-derived input function for brain imaging using the high-resolution research tomograph.
NeuroImage, 2010

Comparison of [11C]-(R)-PK 11195 and [11C]PBR28, two radioligands for translocator protein (18 kDa) in human and monkey: Implications for positron emission tomographic imaging of this inflammation biomarker.
NeuroImage, 2010

Changes of brain phosphodiesterase 4 in major depression.
NeuroImage, 2010

Performance-Constrained Transistor Sizing for Different Cell Count Minimization.
JIP, 2010

Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands.
IPSJ Trans. System LSI Design Methodology, 2010

Performance Estimation with Automatic False-Path Detection for System-Level Designs.
IPSJ Trans. System LSI Design Methodology, 2010

Synthesis and formal verification of on-chip protocol transducers through decomposed specification.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging.
Proceedings of the 28th International Conference on Computer Design, 2010

Polynomial datapath optimization using constraint solving and formal modelling.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SEU tolerant SRAM for FPGA applications.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A debugging method for repairing post-silicon bugs of high performance processors in the fields.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.
Proceedings of the 2010 International Conference on Compilers, 2010

Guided gate-level ATPG for sequential circuits using a high-level test generation approach.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Pipelined Microprocessors Optimization and Debugging.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
A Formal Approach for Debugging Arithmetic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Trends in Formal Verification Techniques for C-based Hardware Designs.
IPSJ Trans. System LSI Design Methodology, 2009

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath.
IEICE Transactions, 2009

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.
IEICE Transactions, 2009

A Unified Framework for Equivalence Verification of Datapath Oriented Applications.
IEICE Transactions, 2009

Functional Equivalence Verification Tools in High-Level Synthesis Flows.
IEEE Design & Test of Computers, 2009

Intelligence Dynamics: a concept and preliminary experiments for open-ended learning agents.
Autonomous Agents and Multi-Agent Systems, 2009

High-level optimization of integer multipliers over a finite bit-width with verification capabilities.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Transaction-based debugging of system-on-chips with patterns.
Proceedings of the 27th International Conference on Computer Design, 2009

Improved heuristics for finite word-length polynomial datapath optimization.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Modular arithmetic decision procedure with auto-correction mechanism.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Polynomial datapath optimization using partitioning and compensation heuristics.
Proceedings of the 46th Design Automation Conference, 2009

Debugging from high level down to gate level.
Proceedings of the 46th Design Automation Conference, 2009

A Post-Silicon Debug Support Using High-Level Design Description.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Brain and whole-body imaging in nonhuman primates of [11C]PBR28, a promising PET radioligand for peripheral benzodiazepine receptors.
NeuroImage, 2008

Kinetic analysis in healthy humans of a novel positron emission tomography radioligand to image the peripheral benzodiazepine receptor, a potential biomarker for inflammation.
NeuroImage, 2008

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation.
JSAT, 2008

3D Perception and Environment Map Generation for Humanoid Robot Navigation.
I. J. Robotics Res., 2008

Custom Instruction Generation with High-Level Synthesis.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Rule-Based Approaches for Equivalence Checking of SpecC Programs.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Arithmetic Circuits Verification without Looking for Internal Equivalences.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

Motion control of a virtual humanoid that can perform real physical interactions with a human.
Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008

A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams.
Proceedings of the ICSOFT 2008, 2008

Adaptive grasping by multi fingered hand with tactile sensor based on robust force and position control.
Proceedings of the 2008 IEEE International Conference on Robotics and Automation, 2008

Multi-level Bounded Model Checking to detect bugs beyond the bound.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Targeting Leakage Constraints during ATPG.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Verification Techniques for System-Level Design.
The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann, ISBN: 978-0-12-370616-4, 2008

2007
Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph.
J. UCS, 2007

Multiscale simulation method for self-organization of nanoparticles in dense suspension.
J. Comput. Physics, 2007

VLSI CAD Education and Exercise Course with Public Domain Tools.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A novel formal approach to generate high-level test vectors without ILP and SAT solvers.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Development and Verification of a Collaborative Printing Environment.
Proceedings of the Fifth International Conference on Creating, 2007

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction.
Proceedings of the Automated Technology for Verification and Analysis, 2007

Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions.
Proceedings of the Automated Technology for Verification and Analysis, 2007

Protocol Transducer Synthesis using Divide and Conquer approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions.
International Journal of Parallel Programming, 2006

Synchronization Verification in System-Level Design with ILP Solvers.
IEICE Transactions, 2006

The AMS Extension to System Level Design Language - SpecC.
IEICE Transactions, 2006

Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment.
IEICE Transactions, 2006

Slicing-based Hardware/Software Co-design Methodology From Functional Specifications.
Electr. Notes Theor. Comput. Sci., 2006

Sequential Equivalence Checking.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Equivalence checking: a rule-based approach.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Dynamically reconfigurable protocol transducer.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

System LSI distributed collaborative design environment for both designers and CAD developers/engineers.
Proceedings of the Fourth International Conference on Creating, 2006

Object-oriented analysis and specification for HW/SW co-design with UML diagrams.
Proceedings of the IASTED International Conference on Advances in Computer Science and Technology, 2006

2005
Autonomous evolution of dynamic gaits with two quadruped robots.
IEEE Trans. Robotics, 2005

Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths.
ACM Trans. Design Autom. Electr. Syst., 2005

An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences.
IEICE Transactions, 2005

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications.
IEICE Transactions, 2005

Synchronization verification in system-level design with ILP solvers.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Extended abstract: a formal design approach from software oriented UML descriptions to hardware oriented RTL.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse.
Proceedings of the 2005 IEEE International Conference on Information Reuse and Integration, 2005

Real-Time Path Planning for Humanoid Robot Navigation.
Proceedings of the IJCAI-05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30, 2005

A Floor and Obstacle Height Map for 3D Navigation of a Humanoid Robot.
Proceedings of the 2005 IEEE International Conference on Robotics and Automation, 2005

A modular architecture for humanoid robot navigation.
Proceedings of the 5th IEEE-RAS International Conference on Humanoid Robots, 2005

System level design language extensions for timed/untimed digital-analog combined system design.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

AMS Extensions for Timed/Untimed System-Level Design Language.
Proceedings of the Forum on specification and Design Languages, 2005

Hexagonal storage scheme for interleaved frame buffers and textures.
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Symposium on Graphics Hardware 2005, 2005

Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
On activating human communications with pet-type robot AIBO.
Proceedings of the IEEE, 2004

High Level Design Validation: Current Practices and Future Directions.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Formal Verification of C Language Based VLSI Designs.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Associated Emotion and Its Expression in an Entertainment Robot QRIO.
Proceedings of the Entertainment Computing, 2004

Behavior selection and motion modulation in emotionally grounded architecture for QRIO SDR-4XII.
Proceedings of the 2004 IEEE/RSJ International Conference on Intelligent Robots and Systems, Sendai, Japan, September 28, 2004

Stair climbing for humanoid robots using stereo vision.
Proceedings of the 2004 IEEE/RSJ International Conference on Intelligent Robots and Systems, Sendai, Japan, September 28, 2004

Behavior Description and Control using Behavior Module for Personal Robot.
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004

Learning behavior selection through interaction based on emotionally grounded symbol concept.
Proceedings of the 4th IEEE/RAS International Conference on Humanoid Robots, 2004

On equivalence checking between behavioral and RTL descriptions.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Precomputed Radiance Transfer with Spatially-Varying Lighting Effects.
Proceedings of the 2004 International Conference on Computer Graphic, 2004

2003
An ethological and emotional basis for human-robot interaction.
Robotics and Autonomous Systems, 2003

An Overview of RoboCup-2002 Fukuoka/Busan.
AI Magazine, 2003

High Presence Remote Presentation in the Shared Immersive Virtual World.
Proceedings of the IEEE Virtual Reality Conference 2003 (VR 2003), 2003

Comparative Study On Verilog-Based And C-Based Hardware Design Education.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Engineering Changes in Field Modifiable Architectures.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

SDR-4X II: A Small Humanoid as an Entertainer in Home Environment.
Proceedings of the Robotics Research, The Eleventh International Symposium, 2003

Autonomous behavior control architecture of entertainment humanoid robot SDR-4X.
Proceedings of the 2003 IEEE/RSJ International Conference on Intelligent Robots and Systems, Las Vegas, Nevada, USA, October 27, 2003

A small biped entertainment robot exploring attractive applications.
Proceedings of the 2003 IEEE International Conference on Robotics and Automation, 2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Model Checking for Dependable Software-Intensive Systems.
Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

Formal verification - prove it or pitch it.
Proceedings of the 40th Design Automation Conference, 2003

Logic optimization for asynchronous speed independent controllers using transduction method.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Irredundant address bus encoding techniques based on adaptive codebooks for low power.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Event-driven observability enhanced coverage analysis of C programs for functional validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Program slicing for VHDL.
STTT, 2002

RoboCup 2001.
IEEE Robot. Automat. Mag., 2002

The road to RoboCup 2050.
IEEE Robot. Automat. Mag., 2002

A Small Biped Entertainment Robot.
JRM, 2002

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.
Formal Methods in System Design, 2002

Simultaneous Circuit Transformation and Routing.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Sony Four Legged Robot League at RoboCup 2002.
Proceedings of the RoboCup 2002: Robot Soccer World Cup VI, 2002

Formal Verification of a Pipelined Processor with New Memory.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Logic Optimization for Asynchronous SI Controllers using Transduction Method.
IWLS, 2002

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.
IWLS, 2002

An equivalence checking methodology for hardware oriented C-based specifications.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Debug methodology for arithmetic circuits on FPGAs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Field modifiable architecture with FPGAs and its design methodology.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams.
Proceedings of the Formal Techniques for Networked and Distributed Systems, 2002

2001
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs.
IEEE Trans. Computers, 2001

AIBO: Toward the Era of Digital Creatures.
I. J. Robotics Res., 2001

Multiresolution Interpolation Meshes.
Proceedings of the 9th Pacific Conference on Computer Graphics and Applications (PG 2001), 2001

New Design Paradigms: What Needs to be Standardized?.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

The standard SpecC language.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Motion entertainment by a small humanoid robot based on OPEN-R.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2001

Ethological Modeling and Architecture for an Entertainment Robot.
Proceedings of the 2001 IEEE International Conference on Robotics and Automation, 2001

Architecture and preliminary experimental results for emotionally grounded symbol acquisition.
Agents, 2001

2000
Vision, Strategy, and Localization Using the Sony Robots at RoboCup-98.
AI Magazine, 2000

Testing, Verification, and Diagnosis in the Presence of Unknowns.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Hierarchical Error Diagnosis Targeting RTL Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Overview of RoboCup-2000.
Proceedings of the RoboCup 2000: Robot Soccer World Cup IV, 2000

Progress in RoboCup Soccer Research in 2000.
Proceedings of the Experimental Robotics VII [ISER 2000, 2000

A quadruped robot platform with basic software for RoboCup-99 legged robot league.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2000

Evolving Robust Gaits with AIBO.
Proceedings of the 2000 IEEE International Conference on Robotics and Automation, 2000

Digital Creatures for Future Entertainment Robotics.
Proceedings of the 2000 IEEE International Conference on Robotics and Automation, 2000

Evolution of Controllers from a High-Level Simulator to a High DOF Robot.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000

Efficient variable ordering using aBDD based sampling.
Proceedings of the 37th Conference on Design Automation, 2000

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.
Proceedings of the 37th Conference on Design Automation, 2000

Automatic partitioning for efficient combinatorial verification.
Proceedings of ASP-DAC 2000, 2000

1999
An efficient filter-based approach for combinational verification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

A reconfigurable robot platform.
Robotics and Autonomous Systems, 1999

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library.
Design Autom. for Emb. Sys., 1999

On the Evaluation of Arbitrary Defect Coverage of Test Sets.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Efficient Scheduling Techniques for ROBDD Construction.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Overview of RoboCup-99.
Proceedings of the RoboCup-99: Robot Soccer World Cup III, 1999

Syntactic-semantic analysis of reconfigurable robot.
Proceedings of the Proceedings 1999 IEEE/RSJ International Conference on Intelligent Robots and Systems. Human and Environment Friendly Robots with High Intelligence and Emotional Quotients, 1999

Speeding Up Look-up-Table Driven Logic Simulation.
Proceedings of the VLSI: Systems on a Chip, 1999

On Reducing Transitions Through Data Modifications.
Proceedings of the 1999 Design, 1999

An Efficient Filter-Based Approach for Combinational Verification.
Proceedings of the 1999 Design, 1999

Multiple Error Diagnosis Based on Xlists.
Proceedings of the 36th Conference on Design Automation, 1999

Symbolic Model Checking Using SAT Procedures instead of BDDs.
Proceedings of the 36th Conference on Design Automation, 1999

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Program Slicing of Hardware Description Languages.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

Model Checking Based on Sequential ATPG.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998
ATM switch design by high-level modeling, formal verification and high-level synthesi.
ACM Trans. Design Autom. Electr. Syst., 1998

Development of an Autonomous Quadruped Robot for Robot Entertainment.
Auton. Robots, 1998

Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A Quadruped Robot for RoboCup Legged Robot Challenge in Paris '98.
Proceedings of the RoboCup-98: Robot Soccer World Cup II, 1998

Modeling the unknown! Towards model-independent fault and error diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Playing soccer with legged robots.
Proceedings of the Proceedings 1998 IEEE/RSJ International Conference on Intelligent Robots and Systems. Innovations in Theory, 1998

Sony Legged Robot for RoboCup Challenge.
Proceedings of the IEEE International Conference on Robotics and Automation, 1998

Sampling schemes for computing OBDD variable orderings.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol.
Proceedings of the Applied Formal Methods, 1998

Using Complementation and Resequencing to Minimize Transitions.
Proceedings of the 35th Conference on Design Automation, 1998

Model Checking: Its Basics and Reality (Embedded Tutorial).
Proceedings of the ASP-DAC '98, 1998

An Open Architecture of Remotion and Behavior Control of Autonomous Agents.
Agents, 1998

Reconfigurable Physical Agents.
Agents, 1998

1997
Power analysis and minimization techniques for embedded DSP software.
IEEE Trans. VLSI Syst., 1997

Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation.
Formal Methods in System Design, 1997

Introduction to the Special Issue on Multi-Terminal Binary Decision Diagrams.
Formal Methods in System Design, 1997

Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping.
Formal Methods in System Design, 1997

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.
Design Autom. for Emb. Sys., 1997

Some Recent Advances in Software and Hardware Logic Simulation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Formal Verification of Combinational Circuit.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Legged Robot for RoboCup Based on "OPENR".
Proceedings of the RoboCup-97: Robot Soccer World Cup I, 1997

A proposal of a quadruped robot platform for RoboCup.
Proceedings of the 1997 IEEE/RSJ International Conference on Intelligent Robot and Systems. Innovative Robotics for Real-World Applications. IROS '97, 1997

A Survey of Techniques for Formal Verification of Combinational Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Formal Verification of the HAL S1 System Cache Coherence Protocol.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Speeding up technology-independent timing optimization by network partitioning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

ATM Switch Design: Parametric High-Level Modeling and Formal Verification.
Proceedings of the Algebraic Methodology and Software Technology, 1997

An Open Architecture for Robot Entertainment.
Agents, 1997

1996
Solving the net matching problem in high-performance chip design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Hybrid Position and Force Control Without Force Sensor.
JRM, 1996

A study of composition schemes for mixed apply/compose based construction of ROBDDs.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On More Efficient Combinational ATPG Using Functional Learning.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions.
ICCAD, 1996

Decomposition Techniques for Efficient ROBDD Construction.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.
Proceedings of the 33st Conference on Design Automation, 1996

Verification of Arithmetic Circuits by Comparing Two Similar Circuits.
Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995
Power analysis and low-power scheduling techniques for embedded DSP software.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Logic synthesis for a single large look-up table.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Simple tree-construction heuristics for the fanout problem .
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Hybrid decision diagrams.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

VERIFUL: VERIfication using FUnctional Learning.
Proceedings of the 1995 European Design and Test Conference, 1995

Advanced Verification Techniques Based on Learning.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

YEPHCAD and FLORA: Logic Synthesis for Control and Datapath.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

LP based cell selection with constraints of timing, area, and power consumption.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A redesign technique for combinational circuits based on gate reconnections.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Bug Identification of a Real Chip Design by Symbolic Model Checking.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Variable ordering algorithms for ordered binary decision diagrams and their evaluation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Motion Planning and Control for a Robot Performer.
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993

Synthesis of Controllers from Interval Temporal Logic Specification.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

An efficient algorithm for the net matching problem.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Force control without force sensor based on mixed sensitivity H design method.
Proceedings of the 1992 IEEE International Conference on Robotics and Automation, 1992

RTL Design Verification by Making Use of Datapath Information.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Rectification method for lookup-table type FPGA's.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Patching Method for Lookup-Table Type FPLs.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

Efficient Sum-to-One Subsets Algorithm for Logic Optimization.
Proceedings of the 29th Design Automation Conference, 1992

1991
Analysis of Neighborhood Interaction in Kohonen Neural Networks.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

Concurrent Resynthesis for Network Optimization.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Application of Boolean Unification to Combinational Logic Synthesis.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis.
Proceedings of the conference on European design automation, 1991

A Resynthesis Approach for Network Optimization.
Proceedings of the 28th Design Automation Conference, 1991

1990
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Practical design assistance at register transfer level using a data path verifier.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Multi-Level Logic Minimization Across Latch Boundaries.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.
Proceedings of the Computer-Aided Verification, 1990

Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989
Logic Design Assistence Using Temporal Logic Based Language Tokio.
Proceedings of the Logic Programming '89, 1989

Multi-level logic optimization using binary decision diagrams.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Evaluation and improvement of Boolean comparison method based on binary decision diagrams.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986
Tokio: Logic Programming Language Based on Temporal Logic and its Compilation to Prolog.
Proceedings of the Third International Conference on Logic Programming, 1986

1985
Implementation of Temporal Logic Programming Language Tokio.
Proceedings of the Logic Programming '85, 1985

Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis.
Proceedings of the Logic Programming '85, 1985

Temporal Logic Programming Language Tokio - Programming in Tokio.
Proceedings of the Logic Programming '85, 1985

1984
Specifying Hardware in temporal Logic & Efficient Synthesis of State-Diagrams Using Prolog.
FGCS, 1984

1983
Temporal Logic Based Hardware Description and Its Verification with Prolog.
New Generation Comput., 1983


  Loading...