P. Pant

According to our database1, P. Pant authored at least 3 papers between 1998 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Innovative practices session 10C: Delay test.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2001
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2001

1998
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998


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