Vivek De

According to our database1, Vivek De authored at least 210 papers between 1996 and 2021.

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Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to low power microprocessor design".

Timeline

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Bibliography

2021
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning.
IEEE J. Solid State Circuits, 2021

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO.
IEEE J. Solid State Circuits, 2020

A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.
IEEE J. Solid State Circuits, 2020

An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop.
IEEE J. Solid State Circuits, 2020

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response.
IEEE J. Solid State Circuits, 2020

A 0.26% BER, 10<sup>28</sup> Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Digital Control of Switching and Linear Integrated Voltage Regulators.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering.
IEEE J. Solid State Circuits, 2019

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors.
IEEE J. Solid State Circuits, 2019

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.
IEEE J. Solid State Circuits, 2019

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies.
IEEE Des. Test, 2019

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019


Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator.
IEEE J. Solid State Circuits, 2018

Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.
CoRR, 2018

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!).
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


F1: Intelligent energy-efficient systems at the edge of IoT.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Exploiting on-chip power management for side-channel security.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.
IEEE J. Solid State Circuits, 2017

A Sub-cm<sup>3</sup> Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications.
IEEE J. Solid State Circuits, 2017

An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS.
IEEE J. Solid State Circuits, 2017

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.
IEEE J. Solid State Circuits, 2017

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators.
J. Hardw. Syst. Secur., 2017

Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era.
IEEE Des. Test, 2017

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.
IEEE J. Solid State Circuits, 2016

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

Energy-Efficient Computing in Nanoscale CMOS.
IEEE Des. Test, 2016

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

F1: Designing secure systems: Manufacturing, circuits and architectures.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

What does ultra low power requirements mean for side-channel secure cryptography?
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions.
IEEE J. Solid State Circuits, 2015

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015

Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.
ACM J. Emerg. Technol. Comput. Syst., 2015

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A 0.4V∼1V 0.2A/mm<sup>2</sup> 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2014

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

Foreword: Welcome to the 2014 Symposium on VLSI Circuits.
Proceedings of the Symposium on VLSI Circuits, 2014

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Energy efficient computing in nanoscale CMOS: Challenges and opportunities.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

Resiliency for many-core system on a chip.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS.
IEEE J. Solid State Circuits, 2013

Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2013

A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
IEEE J. Solid State Circuits, 2013

Adaptive and Resilient Circuits for Dynamic Variation Tolerance.
IEEE Des. Test, 2013

Circuits for resilient systems.
Proceedings of the 3rd Workshop on Fault-tolerance for HPC at extreme scale, 2013

Near-threshold voltage design in nanoscale CMOS.
Proceedings of the Design, Automation and Test in Europe, 2013

Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2012

A fully-digital phase-locked low dropout regulator in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 22nm dynamically adaptive clock distribution for voltage droop tolerance.
Proceedings of the Symposium on VLSI Circuits, 2012

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.
IEEE J. Solid State Circuits, 2011

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits, 2011

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.
IEEE J. Solid State Circuits, 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Energy efficient designs with wide dynamic range.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Serial-Link Bus: A Low-Power On-Chip Bus Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

SRAM dynamic stability estimation using MPFP and its applications.
Microelectron. J., 2009

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits, 2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
IEEE J. Solid State Circuits, 2009

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2009

Circuit techniques for dynamic variation tolerance.
Proceedings of the 46th Design Automation Conference, 2009

2008
Accurate Estimation of SRAM Dynamic Stability.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.
IEEE J. Solid State Circuits, 2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Analytical Model for the Propagation Delay of Through Silicon Vias.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.
VLSI Design, 2007

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A 256-Kb Dual-V<sub>CC</sub> SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
IEEE J. Solid State Circuits, 2007

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Comparative Analysis of Conventional and Statistical Design Techniques.
Proceedings of the 44th Design Automation Conference, 2007

2006
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Impact of Parameter Variations on Circuits and Microarchitecture.
IEEE Micro, 2006

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A 4.2GHz 0.3mm2 256kb Dual-V<sub>cc</sub> SRAM Building Block in 65nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Reducing the Data Switching Activity on Serial Link Buses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reducing the data switching activity of serialized datastreams.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Monolithic voltage conversion in low-voltage CMOS technologies.
Microelectron. J., 2005

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Total power-optimal pipelining and parallel processing under process variations in nanometer technology.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Variation-tolerant circuits: circuit solutions and techniques.
Proceedings of the 42nd Design Automation Conference, 2005

Variations-aware low-power design with voltage scaling.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Low-voltage-swing monolithic dc-dc conversion.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Design optimizations for microprocessors at low temperature.
Proceedings of the 41th Design Automation Conference, 2004

Design and reliability challenges in nanometer technologies.
Proceedings of the 41th Design Automation Conference, 2004

2003
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Multiple-parameter CMOS IC testing with increased sensitivity for I<sub>DDQ</sub>.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Guest editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Compiler Support for Reducing Leakage Energy Consumption.
Proceedings of the 2003 Design, 2003

Parameter variations and impact on circuits and microarchitecture.
Proceedings of the 40th Design Automation Conference, 2003

2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Des. Test Comput., 2002

Challenges in Nanometric Technology Scaling: Trends and Projections.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Evening Panel Discussion: Process Variation: Is It Too Much to Handle?
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Leakage-tolerant design techniques for high performance processors.
Proceedings of 2002 International Symposium on Physical Design, 2002

Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Sub-90nm technologies: challenges and opportunities for CAD.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Life is CMOS: why chase the life after?
Proceedings of the 39th Design Automation Conference, 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002

2001
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Scaling of stack effect and its application for leakage reduction.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low power and high performance design challenges in future technologies.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Dynamic noise analysis in precharge-evaluate circuits.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Technology and design challenges for low power and high performance.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Mixed-<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Intrinsic MOSFET parameter fluctuations due to random dopant placement.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Effects of random MOSFET parameter fluctuations on total power consumption.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI).
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Circuit techniques for low-power CMOS GSI.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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