Jonathon E. Colburn

According to our database, Jonathon E. Colburn authored at least 14 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2019

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.

Seyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn

Proceedings of the IEEE International Test Conference, 2019

2018

XLBIST: X-Tolerant Logic BIST.

Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn

Proceedings of the IEEE International Test Conference, 2018

2017

Test-cost optimization in a scan-compression architecture using support-vector regression.

Zipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Dynamic docking architecture for concurrent testing and peak power reduction.

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.

Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2014

Achieving extreme scan compression for SoC Designs.

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane

Proceedings of the 2014 International Test Conference, 2014

2013

Innovative practices session 10C: Delay test.

P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Innovative practices session 6C: Latest practices in test compression.

Jonathon E. Colburn, K.-Y. Chung, Haluk Konuk, Y. Dong

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Two-level compression through selective reseeding.

Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

Enhancing testability by structured partial scan.

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Hybrid selector for high-X scan compression.

Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn

Proceedings of the 2012 IEEE International Test Conference, 2012

2000

Optimizing Memory Tests by Analyzing Defect Coverage.

Alvin Jee, Jonathon E. Colburn, V. Swamy Irrinki, Mukesh Puri

Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

1999

Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis.

Julie D. Segal, Sergei Bakarian, Jonathon E. Colburn, Madan Kumar, Chang Hong, Alex Shubat

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis.

David B. Lavo, Tracy Larrabee, Jonathon E. Colburn

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999