Panagiotis Sakellariou

According to our database, Panagiotis Sakellariou authored at least 6 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2018

Reconfigurable RO-Path Delay Sensor.

Panagiotis Sakellariou, Vassilis Paliouras

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2016

Application-Specific Low-Power Multipliers.

Panagiotis Sakellariou, Vassilis Paliouras

IEEE Trans. Computers, 2016

2012

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems.

Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikos Kanistras, Ahmed Mahdi, Vassilis Paliouras

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Low-Power Delay Sensors on FPGAs.

Panagiotis Sakellariou, Vassilis Paliouras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Low-power two's-complement multiplication based on selective activation.

Panagiotis Sakellariou, Vassilis Paliouras

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs.

Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012