Vassilis Paliouras
Orcid: 0000-0002-1414-7500Affiliations:
- University of Patras, Greece
According to our database1,
Vassilis Paliouras
authored at least 138 papers
between 1992 and 2023.
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Bibliography
2023
IEEE Trans. Emerg. Top. Comput., 2023
IEEE Trans. Emerg. Top. Comput., 2023
A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case.
Proceedings of the IEEE International Conference on Communications, 2023
Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications.
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels.
IEEE Open J. Commun. Soc., 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2020
Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation.
IEEE Trans. Computers, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE Globecom Workshops, 2020
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations.
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017
Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 25th European Signal Processing Conference, 2017
Work in progress: An introduction to computing course using a Python-based experiential approach.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Signal Process., 2015
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters.
IEEE Trans. Computers, 2013
A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Delay-variation-tolerant FIR filter architectures based on the Residue Number System.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
J. Signal Process. Syst., 2011
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the 8th International Symposium on Wireless Communication Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 17th International Conference on Digital Signal Processing, 2011
Proceedings of the 17th International Conference on Digital Signal Processing, 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information.
J. Signal Process. Syst., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
Proceedings of the Third International Symposium on Wireless Pervasive Computing, 2008
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
2006
Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters.
Proceedings of the 14th European Signal Processing Conference, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A novel architecture and a systematic graph-based optimization methodology for modulo multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Proceedings of the Integrated Circuit and System Design, 2004
An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004
2003
High-radix redundant circuits for RNS modulo r<sup>n</sup>-1, r<sup>n</sup>, or r<sup>n</sup>+1.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
IEEE Trans. Computers, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001
2000
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
A very-long instruction word digital signal processor based on the logarithmic number system.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 23rd EUROMICRO Conference '97, 1997
1996
Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
1995
A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Methodology for the Design of Signed-digit DSP Processors.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
Systematic development of architectures for multidimensional DSP using the residue number system.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992