Ahmed Mahdi

Orcid: 0000-0003-3547-6757

According to our database1, Ahmed Mahdi authored at least 16 papers between 2011 and 2021.

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Bibliography

2021
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2019
Novel Method of Improving Quality of Service for Voice over Internet Protocol Traffic in Mobile Ad Hoc Networks.
Int. J. Commun. Networks Inf. Secur., 2019

2017
Advancing software model-checking by SMT interpolation beyond decidable arithmetic theories: an approach to verify safety properties in embedded and hybrid system models.
PhD thesis, 2017

Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Anthropometric Evaluation of the Design of the Classroom Desk for the Eighth and the Ninth Grades of Benghazi Schools.
Proceedings of the Advances in Physical Ergonomics and Human Factors, 2017

2016
Advancing Software Model Checking Beyond Linear Arithmetic Theories.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Accurate ICP-based floating-point reasoning.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

2015
On the Encoding Complexity of Quasi-Cyclic LDPC Codes.
IEEE Trans. Signal Process., 2015

2014
A Low Complexity-High Throughput QC-LDPC Encoder.
IEEE Trans. Signal Process., 2014

Transformations for Compositional Verification of Assumption-Commitment Properties.
Proceedings of the Reachability Problems - 8th International Workshop, 2014

Generalized Craig Interpolation for Stochastic Satisfiability Modulo Theory Problems.
Proceedings of the Reachability Problems - 8th International Workshop, 2014

2012
Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Digital baseband challenges for a 60GHz gigabit link.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011


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