Massimo Violante
Orcid: 0000-0002-5821-3418
According to our database1,
Massimo Violante
authored at least 168 papers
between 1997 and 2023.
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Bibliography
2023
Towards In-Cabin Monitoring: A Preliminary Study on Sensors Data Collection and Analysis.
CoRR, 2023
An Experimental Evaluation of Control Flow Checking for Automotive Embedded Applications Compliant With ISO 26262.
IEEE Access, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Guidelines for Implementing Control Flow Checking into Automotive Embedded Applications Developed with C Language.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023
Proceedings of the 32nd IEEE International Symposium on Industrial Electronics, 2023
Proceedings of the Eighth International Conference on Fog and Mobile Edge Computing, 2023
A New Approach to Selectively Control Flow Checking Methods Compliant with ISO 26262.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
A Simulation-Based Approach to Aid Development of Software-Based Hardware Failure Detection and Mitigation Algorithms of a Mobile Robot System.
Sensors, 2022
A Novel Redundant Validation IoT System for Affective Learning Based on Facial Expressions and Biological Signals.
Sensors, 2022
Use of Facial Expressions to Improve the Social Acceptance of Level 4 and 5 Automated Driving System Equipped Vehicles.
Proceedings of the 30th International Conference on Software, 2022
Effectiveness of Control Flow Checking Algorithms Using a Model-Based Software Design Approach: An Empirical Study.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2020
Towards Vehicle-Level Simulator Aided Failure Mode, Effect, and Diagnostic Analysis of Automotive Power Electronics Items.
Proceedings of the IEEE Latin-American Test Symposium, 2020
2019
J. Electron. Test., 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 23rd IEEE International Conference on Emerging Technologies and Factory Automation, 2018
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems.
ACM Trans. Embed. Comput. Syst., 2017
J. Electron. Test., 2017
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
J. Electron. Test., 2017
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Deterministic network on chip for deploying real time applications on many-core processors.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Passengers' Emotions Recognition to Improve Social Acceptance of Autonomous Driving Vehicles.
Proceedings of the Advances in Intelligent Information Hiding and Multimedia Signal Processing, 2017
2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables.
Proceedings of the 17th Latin-American Test Symposium, 2016
Online time interference detection in mixed-criticality applications on multicore architectures using performance counters.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
2015
Designing Autonomous Race Car Models for Learning Advanced Topics in Hard Real-Time System.
Int. J. Robotics Appl. Technol., 2015
An Hybrid Architecture for consolidating mixed criticality applications on multicore systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015
2014
Proceedings of the 9th International Design and Test Symposium, 2014
2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Embedded Low Power Controller for Autonomous Landing of UAV Using Artificial Neural Network.
Proceedings of the 10th International Conference on Frontiers of Information Technology, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
An hybrid architecture to detect transient faults in microprocessors: An experimental validation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
IEEE Trans. Ind. Electron., 2011
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.
IEEE Trans. Ind. Electron., 2011
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the ARCS 2011, 2011
Springer, ISBN: 978-1-4419-7594-2, 2011
2010
Boosting software fault injection for dependability analysis of real-time embedded applications.
ACM Trans. Embed. Comput. Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A framework to support the design of COTS-based reliable space computers for on-board data handling.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
A new framework for the automatic insertion of mitigation structures in circuits netlists.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 15th European Test Symposium, 2010
Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
2009
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
A low-cost solution for developing reliable Linux-based space computers for on-board data handling.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
Proceedings of the Design, Automation and Test in Europe, 2009
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electron. Test., 2008
J. Electron. Test., 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices.
Proceedings of the 5th Conference on Computing Frontiers, 2008
2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electron. Test., 2007
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Validating the dependability of embedded systems through fault injection by means of loadable kernel modules.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
IEEE Trans. Computers, 2006
IEEE Trans. Computers, 2006
J. Comput., 2006
IEEE Des. Test Comput., 2006
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
A New Approach to Cope with Single Event Upsets in Processor-based Systems.
Proceedings of the 7th Latin American Test Workshop, 2006
A Fault Injection Environment for SoPC's Embedded Microprocessors.
Proceedings of the 7th Latin American Test Workshop, 2006
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Springer, ISBN: 978-0-387-26060-0, 2006
2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
New evolutionary techniques for test-program generation for complex microprocessor cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.
Proceedings of the 10th European Test Symposium, 2005
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
J. Electron. Test., 2004
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the Applications of Evolutionary Computing, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
Proceedings of the 2004 Design, 2004
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Microelectron. J., 2003
J. Electron. Test., 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.
Proceedings of the 2003 Design, 2003
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
Proceedings of the 2003 Design, 2003
2002
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electron. Test., 2002
A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
System safety through automatic high-level code transformations: an experimental evaluation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the Computer Safety, 2000
Proceedings of the Integrated Circuit Design, 2000
Hardening the Software with Respect to Transient Errors: a Method and Experimental Results.
Proceedings of the 1st Latin American Test Workshop, 2000
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
A genetic algorithm-based system for generating test programs for microprocessor IP cores.
Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 2000
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Proceedings of the Real-World Applications of Evolutionary Computing, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 2000 Design, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Proceedings of the Evolutionary Image Analysis, 1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997