Paolo Grani

Orcid: 0000-0003-3597-2662

According to our database1, Paolo Grani authored at least 13 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2018
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs.
ACM J. Emerg. Technol. Comput. Syst., 2018

2017
Bit-parallel all-to-all and flexible AWGR-based optical interconnects.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip.
Proceedings of the Second International Symposium on Memory Systems, 2016

2015
Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

2014
Design Options for Optical Ring Interconnect in Future Client Devices.
ACM J. Emerg. Technol. Comput. Syst., 2014

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

From hybrid electro-photonic to all-optical on-chip interconnections for future CMPs.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012


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