Davide Bertozzi

According to our database1, Davide Bertozzi authored at least 137 papers between 2002 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
Proceedings of the 2019 International Symposium on Physical Design, 2019

An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
A network model for routing-fault-free wavelength selection in WRONoCs design.
Electron. Notes Discret. Math., 2018

Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs.
Proceedings of the 2018 New Generation of CAS, 2018

CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
IEEE Trans. VLSI Syst., 2017

Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper).
Theory Pract. Log. Program., 2017

Propelling breakthrough embedded microprocessors by means of integrated photonics.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip.
Proceedings of the New Generation of CAS, 2017

Concurrent network-on-chip lifetime testing through selective disconnection of its communication channels.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.
JETC, 2016

Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embedded Comput. Syst., 2015

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
Design Autom. for Emb. Sys., 2015

Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization.
Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
TACO, 2014

Editorial.
Design Autom. for Emb. Sys., 2014

Capturing the sensitivity of optical network quality metrics to its network interface parameters.
Concurrency and Computation: Practice and Experience, 2014

Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Interdisciplinary design of a research experience on microelectronic systems for K-12 students.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Guided Participatory Research on Parallel Computer Architectures for K-12 Students Through a Narrative Approach.
Proceedings of the CSEDU 2014, 2014

A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Enabling power efficiency through dynamic rerouting on-chip.
ACM Trans. Embedded Comput. Syst., 2013

An efficient, low-cost routing framework for convex mesh partitions to support virtualization.
ACM Trans. Embedded Comput. Syst., 2013

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embedded Comput. Syst., 2013

Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip.
IET Computers & Digital Techniques, 2013

System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
Proceedings of the 2013 International Symposium on System on Chip, 2013

PROTON: an automatic place-and-route tool for optical networks-on-chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

Topic 13: High-Performance Networks and Communication - (Introduction).
Proceedings of the Euro-Par 2013 Parallel Processing, 2013

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis.
Proceedings of the Design, Automation and Test in Europe, 2013

A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
IJERTCS, 2012

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Ultra-low latency NoC testing via pseudo-random test pattern compaction.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Power efficiency of switch architecture extensions for fault tolerant NoC design.
Proceedings of the 2012 International Green Computing Conference, 2012

Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.
IJERTCS, 2011

Variability compensation for full-swing against low-swing on-chip communication.
IET Computers & Digital Techniques, 2011

Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff.
Embedded Systems Letters, 2011

System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Bringing Network-on-Chip links to 45nm.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Proceedings of the Design, Automation and Test in Europe, 2011

Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.
Proceedings of the NOCS 2010, 2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.
Proceedings of the NOCS 2010, 2010

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Efficient implementation of distributed routing algorithms for NoCs.
IET Computers & Digital Techniques, 2009

Networks on chips [editorial].
IET Computers & Digital Techniques, 2009

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.
Proceedings of the Design, Automation and Test in Europe, 2009

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.
Proceedings of the Embedded Systems Design and Verification, 2009

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2008

A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.
International Journal of Parallel Programming, 2008

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.
Proceedings of the Logic Programming, 24th International Conference, 2008

Network Interface Sharing Techniques for Area Optimized NoC Architectures.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.
Proceedings of the Design, Automation and Test in Europe, 2008

Variation tolerant NoC design by means of self-calibrating links.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Networks-on-Chip: Emerging Research Topics and Novel Ideas.
VLSI Design, 2007

Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.
Trans. HiPEAC, 2007

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.
IEEE Trans. Computers, 2007

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Supporting task migration in multi-processor systems-on-chip: a feasibility study.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
Proceedings of the 43rd Design Automation Conference, 2006

Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs.
Proceedings of the Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, 2006

MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
State-of-the-Art SoC Communication Architectures.
Proceedings of the Embedded Systems Handbook., 2005

Network-on-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Embedded Systems Handbook., 2005

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.
VLSI Signal Processing, 2005

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2005

Error control schemes for on-chip communication links: the energy-reliability tradeoff.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip.
Intelligenza Artificiale, 2005

Fault tolerance overhead in network-on-chip flow control schemes.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
Proceedings of the 2005 Design, 2005

Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation.
Proceedings of the Principles and Practice of Constraint Programming, 2005

Network On-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Analyzing On-Chip Communication in a MPSoC Environment.
Proceedings of the 2004 Design, 2004

Energy-Efficient Network-On-Chip Design.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Performance Analysis of Arbitration Policies for SoC Communication Architectures.
Design Autom. for Emb. Sys., 2003

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.
IEEE Computer, 2003

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
Proceedings of the 2003 Design, 2003

Energy-Reliability trade-Off for NoCs.
Proceedings of the Networks on Chip, 2003

2002
Power aware network interface management for streaming multimedia.
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002

Parametric timing and power macromodels for high level simulation of low-swing interconnects.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Low Power Error Resilient Encoding for On-Chip Data Buses.
Proceedings of the 2002 Design, 2002


  Loading...