Frédéric Paillardet

According to our database, Frédéric Paillardet authored at least 5 papers between 2008 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Sequential Dual-Loop Digital and Analog PLL Synthesizer for Fast-Locking IoT Applications in 18nm FD-SOI CMOS.

Virgile Colrat, David Gaidioz, Andres Asprilla, Frédéric Paillardet, Andreia Cathelin, Yann Deval

Proceedings of the 17th IEEE Latin America Symposium on Circuits and System, 2026

A 1.16GHz -160.4dBFS/Hz-NSD multi-bit Continuous-Time Delta-Sigma ADC Achieving SNR/SNDR of 86dB/83dB in 17.5MHz-BW without DAC calibration.

Vaibhav Garg, Paras Garg, Ankur Bal, Sanyam Jain, Frédéric Paillardet, Kallol Chatterjee, Chandrajit Debnath, Gauri Mittal, Anand Kumar

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2021

An hybrid approach for high-performance passive 120-GHz phase shifters in BiCMOS technology.

David Ouattara, Cedric Durand, Philippe Ferrari, Sylvain Bourdel, Frédéric Paillardet

Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

2008

A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS.

Franck Montaudon, Rayan Mina, Stéphane Le Tual, Loic Joët, Daniel Saias, Razak Hossain, Florent Sibille, Christian Corre, Valerie Carrat, Emmanuel Chataigner, Jerome Lajoinie, Sébastien Dedieu, Frédéric Paillardet, Ernesto Perea

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS.

Mounir Boulemnakher, Eric Andre, Jocelyn Roux, Frédéric Paillardet

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008