Parit Kanjanavirojkul

According to our database, Parit Kanjanavirojkul authored at least 5 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Impulse signal generator based on current-mode excitation and transmission line resonator.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

CMOS-on-quartz pulse generator for low power applications.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2014

Burst-pulse Generator based on transmission line toward sub-MMW.

Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014