Tetsuya Iizuka

According to our database1, Tetsuya Iizuka authored at least 86 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Theoretical Analysis of Noise Figure for Modulated Wideband Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS.
IET Circuits Devices Syst., 2020

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field.
IEEE Trans. Instrum. Meas., 2019

A 140 GHz area-and-power-efficient VCO using frequency doubler in 65 nm CMOS.
IEICE Electron. Express, 2019

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.
IEICE Electron. Express, 2019

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
IEICE Electron. Express, 2019

A 0.0053-mm<sup>2</sup> 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation.
IEEE Trans. Instrum. Meas., 2018

Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting.
IEICE Trans. Electron., 2018

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction.
IEICE Trans. Electron., 2018

A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit.
IEICE Trans. Electron., 2018

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Time-domain approach for analog circuits in deep sub-micron LSI.
IEICE Electron. Express, 2018

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring.
IEICE Trans. Electron., 2017

A PLL Compiler from Specification to GDSII.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Impulse signal generator based on current-mode excitation and transmission line resonator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017

High Spatial Resolution Detection Method for Point Light Source in Scintillator.
Proceedings of the Computational Imaging XV, Burlingame, 2017

Session 4 - Modeling and measurement of mixed-signal circuits.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

CMOS-on-quartz pulse generator for low power applications.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors.
J. Circuits Syst. Comput., 2016

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016

Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Resonant power supply noise reduction using a triangular active charge injection.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Analytical design optimization of sub-ranging ADC based on stochastic comparator.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs.
IEEE Trans. Instrum. Meas., 2015

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015

F1: High-speed interleaved ADCs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Session 3 - Optical interconnect and reliability enhancement techniques.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

High-resolution measurement of magnetic field generated from cryptographic LSIs.
Proceedings of the IEEE Sensors Applications Symposium, 2014

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Session 26 overview: High-speed data converters.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.
Proceedings of the International Symposium on Physical Design, 2013

A Pulse Width controlled PLL and its automated design flow.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme.
IEICE Trans. Electron., 2012

A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology.
IEICE Trans. Electron., 2012

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator.
IEICE Trans. Electron., 2012

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Impact of All-Digital PLL on SoC Testing.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Cascaded Time Difference Amplifier with Differential Logic Delay Cell.
IEICE Trans. Electron., 2011

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells.
IEICE Trans. Electron., 2011

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.
IEICE Trans. Electron., 2011

All-digital ramp waveform generator for two-step single-slope ADC.
IEICE Electron. Express, 2011

A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Time-to-digital converter based on time difference amplifier with non-linearity calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2007
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Timing-driven cell layout de-compaction for yield optimization by critical area minimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Exact minimum-width transistor placement without dual constraint for CMOS cells.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2000
Mining sequential patterns including time intervals.
Proceedings of the Data Mining and Knowledge Discovery: Theory, 2000

1998
Automatic Visualization Method for Visual Data Mining.
Proceedings of the Research and Development in Knowledge Discovery and Data Mining, 1998


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