Tetsuya Iizuka
Orcid: 0000-0002-1512-4714
According to our database1,
Tetsuya Iizuka
authored at least 111 papers
between 1998 and 2023.
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Bibliography
2023
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Long-time-constant leaky-integrating oxygen-vacancy drift-diffusion FET for human-interactive spiking reservoir computing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit.
Proceedings of the International Conference on IC Design and Technology, 2023
Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction.
Proceedings of the International Conference on IC Design and Technology, 2023
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit.
Proceedings of the International Conference on IC Design and Technology, 2023
2022
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop.
IEICE Trans. Electron., October, 2022
Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
High-Precision Sub-Nyquist Sampling System Based on Modulated Wideband Converter for Communication Device Testing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
CMOS-based area-and-power-efficient neuron and synapse circuits for time-domain analog spiking neural networks.
CoRR, 2022
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
140 GHz Energy-Efficient OOK Receiver using Self-Mixer-Based Power Detector in 65nm CMOS.
Proceedings of the International Conference on IC Design and Technology, 2022
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper.
Proceedings of the International Conference on IC Design and Technology, 2021
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS.
IET Circuits Devices Syst., 2020
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing.
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field.
IEEE Trans. Instrum. Meas., 2019
IEICE Electron. Express, 2019
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.
IEICE Electron. Express, 2019
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
IEICE Electron. Express, 2019
A 0.0053-mm<sup>2</sup> 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
2018
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation.
IEEE Trans. Instrum. Meas., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEICE Trans. Electron., 2018
IEICE Trans. Electron., 2018
A Unified Analysis of the Signal Transfer Characteristics of a Single-Path FET-R-C Circuit.
IEICE Trans. Electron., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEICE Electron. Express, 2018
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
IEICE Trans. Electron., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Impulse signal generator based on current-mode excitation and transmission line resonator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Computational Imaging XV, Burlingame, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors.
J. Circuits Syst. Comput., 2016
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs.
IEEE Trans. Instrum. Meas., 2015
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the IEEE Sensors Applications Symposium, 2014
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.
Proceedings of the International Symposium on Physical Design, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme.
IEICE Trans. Electron., 2012
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology.
IEICE Trans. Electron., 2012
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator.
IEICE Trans. Electron., 2012
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation.
J. Next Gener. Inf. Technol., 2011
IEICE Trans. Electron., 2011
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells.
IEICE Trans. Electron., 2011
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.
IEICE Trans. Electron., 2011
IEICE Electron. Express, 2011
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Time-to-digital converter based on time difference amplifier with non-linearity calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2007
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Timing-driven cell layout de-compaction for yield optimization by critical area minimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2000
Proceedings of the Data Mining and Knowledge Discovery: Theory, 2000
1998
Proceedings of the Research and Development in Knowledge Discovery and Data Mining, 1998