Paritosh Bhoraskar

Orcid: 0000-0002-4352-9698

According to our database1, Paritosh Bhoraskar authored at least 7 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration.
IEEE J. Solid State Circuits, 2020

16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration.
IEEE J. Solid State Circuits, 2014

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2010
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration.
IEEE J. Solid State Circuits, 2010

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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