Mike Hensley

According to our database, Mike Hensley authored at least 5 papers between 2000 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm.

Haiyang Zhu, Larry Singer, Ron Kapusta, Dan Kelly, Tao Pan, Mike Hensley, Scott Bardsley, Christopher Dillon, Daniel Rey-Losada, Kashif M. Sheikh, Chen-Kai Hsu, Zhao Li, Janet Brunsilius, Enrique Alvarez-Fontecilla, Robert Bishop, Paul Wilkins, Hassan L'Bahy, Adalberto Cantoni, Nuo Zhang, Kaung Myat San Oo, Cihan Asci

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2010

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration.

Ahmed M. A. Ali, Andrew S. Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Paritosh Bhoraskar, Hüseyin Dinc, Mike Hensley, Russell Stop, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed

IEEE J. Solid State Circuits, 2010

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration.

Ahmed M. A. Ali, Andy Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2004

A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver].

Mike Hensley, Carroll Speir, Russell Stop, Kevin Behel, Carl Moreland, Greg Patterson, Dan Kelly, Manish Manglani, Michael Elliott, Scott Puckett, Joe Young, Frank Murden

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000

A 14-bit 100-Msample/s subranging ADC.

Carl Moreland, Frank Murden, Michael Elliott, Joe Young, Mike Hensley, Russell Stop

IEEE J. Solid State Circuits, 2000