Janet Brunsilius

According to our database, Janet Brunsilius authored at least 8 papers between 2006 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm.

Haiyang Zhu, Larry Singer, Ron Kapusta, Dan Kelly, Tao Pan, Mike Hensley, Scott Bardsley, Christopher Dillon, Daniel Rey-Losada, Kashif M. Sheikh, Chen-Kai Hsu, Zhao Li, Janet Brunsilius, Enrique Alvarez-Fontecilla, Robert Bishop, Paul Wilkins, Hassan L'Bahy, Adalberto Cantoni, Nuo Zhang, Kaung Myat San Oo, Cihan Asci

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET.

Junhua Shen, Wei-Hung Chen, Efram Burlingame, Stephen Weinreich, Michael Elliott, Stuart McCracken, Jack Kenney, Janet Brunsilius, Anil Korkmaz, Enrique Alvarez-Fontecilla, Nevena Rakuljic, Ushma Mehta, Ben Sullivan, Jeremy Scuteri, Bac Binh Luu, Mitchell Nichols, Dara Martin, Richard Sullivan, Daniel DeBolt, Ron Kapusta

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2017

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.

Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro

IEEE J. Solid State Circuits, 2017

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology.

Siddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2014

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Russell Stop

IEEE J. Solid State Circuits, 2014

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration.

Ahmed M. Abdelatty Ali, Hüseyin Dinc, Paritosh Bhoraskar, Christopher Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, David Jarman, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea, Ho-Young Lee

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2011

A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC.

Janet Brunsilius, Eric Siragusa, Steve Kosic, Frank Murden, Ege Yetis, Binh Luu, Jeff Bray, Phil Brown, Allen Barlow

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2006

A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points.

Tony Montalvo, C. Angell, David J. McLaurin, Corey Petersen, Eric Fogleman, Janet Brunsilius, Phil Brown, Ege Yetis, Jeff Bray, M. Kessler, Bernard Tenbroek

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006