Partha De

Orcid: 0000-0003-0494-2030

According to our database1, Partha De authored at least 6 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
Secure Path Balanced BDD-Based Pre-Charge Logic for Masking.
IEEE Trans. Circuits Syst., 2020

2019
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2016
Heuristics for 2-coverage multi point relay problem in wireless ad hoc and sensor networks.
Proceedings of the 14th International Symposium on Modeling and Optimization in Mobile, 2016

2014
A BDD based secure hardware design method to guard against power analysis attacks.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013


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