Chittaranjan Mandal

According to our database, Chittaranjan Mandal authored at least 22 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Energy-Aware Service Allocation: A Crow Search-Based Approach.

Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal

IEEE Trans. Green Commun. Netw., March, 2023

SeamFlow: Seamless Flow Forwarding in Energy Harvesting-Enabled Access Points of SDWLAN.

Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal, Samaresh Bera

IEEE Trans. Sustain. Comput., 2023

2022

ETHoS: Energy-Aware Traffic Engineering for Sustainable Hybrid SDN.

Ilora Maity, Sudip Misra, Chittaranjan Mandal

IEEE Trans. Sustain. Comput., 2022

Sustainable Maintenance of Connected Dominating Set by Solar Energy Harvesting for IoT Networks.

Chandrani Ray Chowdhury, Chittaranjan Mandal, Sudip Misra

IEEE Trans. Green Commun. Netw., 2022

Clustering Based Parameter Estimation of Thyroid Hormone Pathway.

Devleena Ghosh, Chittaranjan Mandal

IEEE ACM Trans. Comput. Biol. Bioinform., 2022

SCOPE: Cost-Efficient QoS-Aware Switch and Controller Placement in Hybrid SDN.

Ilora Maity, Sudip Misra, Chittaranjan Mandal

IEEE Syst. J., 2022

IEEE 802.11k-Based Lightweight, Distributed, and Cooperative Access Point Coverage Estimation Scheme in IoT Networks.

Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal

IEEE Internet Things J., 2022

2021

Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan.

Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris

IEEE Trans. Intell. Transp. Syst., 2021

CORE: Prediction-Based Control Plane Load Reduction in Software-Defined IoT Networks.

Ilora Maity, Sudip Misra, Chittaranjan Mandal

IEEE Trans. Commun., 2021

DART: Data Plane Load Reduction for Traffic Flow Migration in SDN.

Ilora Maity, Sudip Misra, Chittaranjan Mandal

IEEE Trans. Commun., 2021

2020

Secure Path Balanced BDD-Based Pre-Charge Logic for Masking.

Partha De, Udaya Parampalli, Chittaranjan Mandal

IEEE Trans. Circuits Syst., 2020

Double electron capture in fast ion-atom collisions.

Saheb Halder, Subhajit Samaddar, Karunamoy Purkait, Abhoy Mondal, Chittaranjan R. Mandal, Malay Purkait

J. Comput. Methods Sci. Eng., 2020

Traffic-Aware Consistent Flow Migration in SDN.

Ilora Maity, Sudip Misra, Chittaranjan Mandal

Proceedings of the 2020 IEEE International Conference on Communications, 2020

2019

Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks.

Partha De, Chittaranjan Mandal, Udaya Parampalli

IEEE Trans. Very Large Scale Integr. Syst., 2019

Tensor-Based Rule-Space Management System in SDN.

Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal

IEEE Syst. J., 2019

2018

CURE: Consistent Update With Redundancy Reduction in SDN.

Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal

IEEE Trans. Commun., 2018

2017

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs.

Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta

Integr., 2017

2015

Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool.

Gargi Roy, Devleena Ghosh, Chittaranjan Mandal, Indraneel Mitra

Proceedings of the Seventh IEEE International Conference on Technology for Education, 2015

A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization.

Gargi Roy, Devleena Ghosh, Chittaranjan Mandal

Proceedings of the Seventh IEEE International Conference on Technology for Education, 2015

Layout Validation Using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification.

Devleena Ghosh, Chittaranjan Mandal

Proceedings of the 2015 Asia-Pacific Software Engineering Conference, 2015

2013

Re-using Refresh for Self-Testing DRAMs.

Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2006

Asynchronous Design Methodology for an Efficient Implementation of Low power ALU.

Palanichamy Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, Chittaranjan R. Mandal

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006