Chittaranjan A. Mandal

According to our database1, Chittaranjan A. Mandal authored at least 77 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Equivalence checking of Petri net models of programs using static and dynamic cut-points.
Acta Inf., 2019

SamaTulyataOne: A Path Based Equivalence Checker.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2017
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers.
IEEE Trans. Software Eng., 2017

Deriving bisimulation relations from path based equivalence checkers.
Formal Asp. Comput., 2017

Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information.
Computer Networks, 2017

An Equivalence Checking Framework for Array-Intensive Programs.
Proceedings of the Automated Technology for Verification and Analysis, 2017

SamaTulyata: An Efficient Path Based Equivalence Checking Tool.
Proceedings of the Automated Technology for Verification and Analysis, 2017

2016
A Path Construction Algorithm for Translation Validation Using PRES+ Models.
Parallel Processing Letters, 2016

Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set.
Ad Hoc Networks, 2016

A Novel EPE Aware Hybrid Global Route Planner after Floorplanning.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An early global routing framework for uniform wire distribution in SoCs.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Translation validation of loop and arithmetic transformations in the presence of recurrences.
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

An efficient path based equivalence checking for Petri net based models of programs.
Proceedings of the 9th India Software Engineering Conference, 2016

2015
Determining Equivalence of Expressions: An Automated Evaluator's Perspective.
Proceedings of the Seventh IEEE International Conference on Technology for Education, 2015

A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs.
Proceedings of the 15th IEEE International Working Conference on Source Code Analysis and Manipulation, 2015

Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective.
Proceedings of the Mining Intelligence and Knowledge Exploration, 2015

A New Method for Defining Monotone Staircases in VLSI Floorplans.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating SPARK: High Level Synthesis Compiler.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Path-based Equivalence Checking Method for Petri Net based Models of Programs.
Proceedings of the ICSOFT-EA 2015, 2015

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2014
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Verification of Code Motion Techniques Using Value Propagation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Global Routing Using Monotone Staircases with Minimal Bends.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A BDD based secure hardware design method to guard against power analysis attacks.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Verification of KPN Level Transformations.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

STAIRoute: Global routing using monotone staircase channels.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results.
Proceedings of the 19th International Conference on Management of Data, 2013

2012
Formal verification of code motion techniques using data-flow-driven equivalence checking.
ACM Trans. Design Autom. Electr. Syst., 2012

POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
J. Low Power Electronics, 2012

A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Workload Driven Power Domain Partitioning.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.
VLSI Design, 2011

An improved greedy construction of minimum connected dominating sets in wireless networks.
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011

Verification of Register Transfer Level Low Power Transformations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
Proceedings of the International Symposium on Electronic System Design, 2011

2010
Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks.
IEEE Trans. Parallel Distrib. Syst., 2010

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.
Integration, 2010

A BDD-based approach to design power-aware on-line detectors for digital circuits.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009
Efficient clusterhead rotation via domatic partition in self-organizing sensor networks.
Wireless Communications and Mobile Computing, 2009

Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks.
IEEE Trans. Mob. Comput., 2009

Systematic Methodology for High-Level Performance Modeling of Analog Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Location Updates of Mobile Node in Wireless Sensor Networks.
Proceedings of the MSN 2009, 2009

2008
A Fast Exploration Procedure for Analog High-Level Specification Translation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

2007
A System for Automatic Evaluation of C Programs: Features and Interfaces.
IJWLTT, 2007

Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash.
Proceedings of the WEBIST 2007, 2007

Automatic Detection of Human Fall in Video.
Proceedings of the Pattern Recognition and Machine Intelligence, 2007

Register Sharing Verification During Data-Path Synthesis.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks.
Proceedings of the Second International Conference on COMmunication System softWAre and MiddlewaRE (COMSWARE 2007), 2007

2006
Animating Algorithms over the Web.
Proceedings of the WEBIST 2006, 2006

A System for Automatic Evaluation of Programs for Correctness and Performance.
Proceedings of the Web Information Systems and Technologies, International Conferences, 2006

A System for Automatic Evaluation of Programs for Correctness and Performance.
Proceedings of the WEBIST 2006, 2006

Verification of Scheduling in High-level Synthesis.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A formal approach for high level synthesis of linear analog systems.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic.
Proceedings of the 2004 Design, 2004

2002
Timing analysis of tree-like RLC circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.
IEEE Trans. VLSI Syst., 2000

A Genetic Algorithm for the Synthesis of Structured Data Paths.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
A design space exploration scheme for data-path synthesis.
IEEE Trans. VLSI Syst., 1999

1998
Complexity of Scheduling in High Level Synthesis.
VLSI Design, 1998

1997
Design Space Exploration for Data Path Synthesis.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1992
Interconnect Optimization Techniques in Data Path Synthesis.
Proceedings of the Fifth International Conference on VLSI Design, 1992


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