Patchara Sawakewang

According to our database, Patchara Sawakewang authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations.

Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, April, 2025

2024

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling.

Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024