Sayan Kumar

According to our database, Sayan Kumar authored at least 7 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 24.5-45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation.

Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon

IEEE J. Solid State Circuits, April, 2026

2025

Asymmetry Effects on Thermal and Flicker Phase Noise of Rotary Traveling-Wave Oscillators.

Sayan Kumar, Chawin Khongprasongsiri, Tomas Sarapas, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Teerachot Siriburanon, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. II Express Briefs, December, 2025

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations.

Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, April, 2025

A 4kb 4T eDRAM with Balanced Retention Time Adjustment.

Sayan Kumar, Dennis Andrade-Miceli, Chawin Khongprasongsiri, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Trifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range.

Sumit Dash, Sayan Kumar, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling.

Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm.

Animesh Gupta, Sayan Kumar, Viveka Konandur Rajanna, Sachin Taneja, Massimo Alioto

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023