Khurram Muhammad

IEEE J. Solid State Circuits, 2010

2009

Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Design of Sigma-Delta Modulators With Arbitrary Transfer Functions.

[BibT_eX]

[DOI]

Yongtao Wang

IEEE Trans. Signal Process., 2007

IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Verification of Digital RF Processors: RF, Analog, Baseband, and Software.

[BibT_eX]

[DOI]

Thomas Murphy

IEEE J. Solid State Circuits, 2007

On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Layout-driven architecture synthesis for high-speed digital filters.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

IIP2 and DC Offsets in the Presence of Leakage at LO Frequency.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Efficient modeling of 1/falpha/ noise using multirate process.

[BibT_eX]

[DOI]

Jongsun Park

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS.

[BibT_eX]

[DOI]

Jinseok Koh

Gabriel Gomez

Baher Haroun

EURASIP J. Wirel. Commun. Netw., 2006

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers.

[BibT_eX]

[DOI]

Yo-Chuol Ho

EURASIP J. Wirel. Commun. Netw., 2006

Digital RF Processor Techniques for Single-Chip Radios.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Digital Signal Processing for RF at 45-nm CMOS and Beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

All-digital PLL and transmitter for mobile phones.

[BibT_eX]

[DOI]

Sudheer K. Vemulapalli

IEEE J. Solid State Circuits, 2005

Digital RF processing: toward low-cost reconfigurable radios.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2005

Digital RF Processing Techniques for SoC Radios, invited.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Digital RF processor (DRP™) for cellular phones.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D converters.

[BibT_eX]

[DOI]

Tom Jung

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Complexity reduction of digital filters using shift inclusive differential coefficients.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2004

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Direct RF sampling mixer with recursive filtering in charge domain.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process.

[BibT_eX]

[DOI]

Jinseok Koh

Gabriel Gomez

Baher Horoun

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

High-performance FIR filter design based on sharing multiplication.

[BibT_eX]

[DOI]

Jongsun Park

IEEE Trans. Very Large Scale Integr. Syst., 2003

Two's complement computation sharing multiplier and its applications to high performance DFE.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2003

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Efficient generation of 1/fα noise using a multi-rate filter bank.

[BibT_eX]

[DOI]

Jongsun Park

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Spatial averaging and ordering in matched element arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.

[BibT_eX]

[DOI]

Lih-Yih Chiou

VLSI Design, 2001

Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2001

Fault Detection and Location Using IDD Waveform Analysis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

Decision feedback equalizer with two's complement computation sharing multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

DSP data path synthesis for low-power applications.

[BibT_eX]

[DOI]

Lih-Yih Chiou

Proceedings of the IEEE International Conference on Acoustics, 2001

Challenges in integrated CMOS transceivers for short distance wireless.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Low complexity FIR filters using factorization of perturbed coefficients.

[BibT_eX]

[DOI]

Cassondra Neau

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

Low Power VLSI Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Non-adaptive and adaptive filter implementation based on sharing multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2000

Minimally redundant parallel implementation of digital filters and vector scaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2000

1999

A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on System Synthesis, 1999

Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.

[BibT_eX]

[DOI]

Dinesh Somasekhar

Proceedings of the IEEE International Conference On Computer Design, 1999

A novel design methodology for high performance and low power digital filters.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

High-level modeling of switching activity with application to low-power DSP system synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1997

Fast Simulation of DS/CDMA With and Without Coding in Multipath Fading Channels.

[BibT_eX]

[DOI]

Khaled Ben Letaief

John S. Sadowsky

IEEE J. Sel. Areas Commun., 1997

On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995

On the performance of sequential and Viterbi decoders for high-rate punctured convolutional codes.

[BibT_eX]

[DOI]

Khaled Ben Letaief

IEEE Trans. Commun., 1995

An efficient new technique for accurate bit error probability estimation of ZJ decoders.

[BibT_eX]

[DOI]

Khaled Ben Letaief