Teerachot Siriburanon

According to our database1, Teerachot Siriburanon authored at least 42 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance.
IEEE J. Solid State Circuits, 2019

A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

A Low-Flicker-Noise 30-GHz Class-F<sub>23</sub> Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path.
IEEE J. Solid State Circuits, 2018

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS.
IEICE Trans. Electron., 2018

2017
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.
IEEE J. Solid State Circuits, 2017

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f<sup>3</sup> corner.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017


2016
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits, 2016

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.
IEEE J. Solid State Circuits, 2016

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.
IEEE J. Solid State Circuits, 2015

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit.
IEICE Trans. Electron., 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

14.1 A 0.048mm<sup>2</sup> 3mW synthesizable fractional-N PLL with a soft injection-locking technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.
Proceedings of the ESSCIRC Conference 2015, 2015

An HDL-synthesized gated-edge-injection PLL with a current output DAC.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration.
IEEE J. Solid State Circuits, 2014

15.1 A 0.0066mm<sup>2</sup> 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers.
IEEE J. Solid State Circuits, 2013

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer.
IEICE Trans. Electron., 2013

A 0.022mm<sup>2</sup> 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers.
Proceedings of the 38th European Solid-State Circuit conference, 2012


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