Patrick B. Moran

According to our database¹, Patrick B. Moran authored at least 2 papers between 2006 and 2007.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2007

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

2006

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Patrick B. Moran

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