Hyunwoo Lee
Affiliations:- Korea University, Department of Electronics and Electrical Engineering, Seoul, Korea
- SK Hynix semiconductor Inc., Hyundai Electronics, Icheon, Korea
According to our database1,
Hyunwoo Lee authored at least 21 papers
between 2006 and 2018.
Collaborative distances:
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Bibliography
2018
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2015
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Springer Briefs in Electrical and Computer Engineering, Springer, ISBN: 978-3-319-02381-6, 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface.
IEEE J. Solid State Circuits, 2013
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.
IEEE J. Solid State Circuits, 2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEICE Electron. Express, 2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Proceedings of the ESSCIRC 2008, 2008
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006