Jaehoon Cha
Orcid: 0000-0002-2498-4214
According to our database1,
Jaehoon Cha
authored at least 15 papers
between 2007 and 2024.
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Bibliography
2024
Feature-Action Design Patterns for Storytelling Visualizations with Time Series Data.
CoRR, 2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Geosci. Remote. Sens., 2023
Orthogonality-Enforced Latent Space in Autoencoders: An Approach to Learning Disentangled Representations.
Proceedings of the International Conference on Machine Learning, 2023
2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
A hierarchical auxiliary deep neural network architecture for large-scale indoor localization based on Wi-Fi fingerprinting.
Appl. Soft Comput., 2022
2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
2019
Data Gathering and Application to Building Energy Optimization with Sensitivity Analysis for IoT Applications.
Proceedings of the 2019 International SoC Design Conference, 2019
2017
Large-Scale Location-Aware Services in Access: Hierarchical Building/Floor Classification and Location Estimation using Wi-Fi Fingerprinting Based on Deep Neural Networks.
CoRR, 2017
Proceedings of the Joint 17th World Congress of International Fuzzy Systems Association and 9th International Conference on Soft Computing and Intelligent Systems, 2017
2007
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.
IEEE J. Solid State Circuits, 2007