Jaehoon Cha

Orcid: 0000-0002-2498-4214

According to our database1, Jaehoon Cha authored at least 21 papers between 2007 and 2026.

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Bibliography

2026
Enhancing rainfall prediction accuracy through image fusion of radar and numerical weather prediction models.
Expert Syst. Appl., 2026

15.9 A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

Token-Wise Kernels (TWiKers) for Vicinity-Aware Attention in Transformers.
Proceedings of the Findings of the Association for Computational Linguistics: EACL 2026, 2026

2025
Discovering fully semantic representations via centroid- and orientation-aware feature learning.
Nat. Mac. Intell., 2025

Enhancing Imaging Generation through Implicit Neural Representations and HyperNetwork for Spatial Variability.
Proceedings of the 2025 IEEE International Conference on Acoustics, 2025

2024
Deep Learning Evidence for Global Optimality of Gerver's Sofa.
Symmetry, 2024

Feature-Action Design Patterns for Storytelling Visualizations with Time Series Data.
CoRR, 2024

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Deep Learning-Based Rainfall Prediction Using Cloud Image Analysis.
IEEE Trans. Geosci. Remote. Sens., 2023

Orthogonality-Enforced Latent Space in Autoencoders: An Approach to Learning Disentangled Representations.
Proceedings of the International Conference on Machine Learning, 2023

2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022

Disentangling Autoencoders (DAE).
CoRR, 2022

A hierarchical auxiliary deep neural network architecture for large-scale indoor localization based on Wi-Fi fingerprinting.
Appl. Soft Comput., 2022

2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Hierarchical Auxiliary Learning.
Mach. Learn. Sci. Technol., 2020

2019
On the Transformation of Latent Space in Autoencoders.
CoRR, 2019

Data Gathering and Application to Building Energy Optimization with Sensitivity Analysis for IoT Applications.
Proceedings of the 2019 International SoC Design Conference, 2019

2017
Analysis of a Similarity Measure for Non-Overlapped Data.
Symmetry, 2017

Large-Scale Location-Aware Services in Access: Hierarchical Building/Floor Classification and Location Estimation using Wi-Fi Fingerprinting Based on Deep Neural Networks.
CoRR, 2017

On the design of similarity measures based on fuzzy integral.
Proceedings of the Joint 17th World Congress of International Fuzzy Systems Association and 9th International Conference on Soft Computing and Intelligent Systems, 2017

2007
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.
IEEE J. Solid State Circuits, 2007


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