Yongsuk Joo
According to our database1,
Yongsuk Joo
authored at least 7 papers
between 2007 and 2024.
Collaborative distances:
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Bibliography
2024
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2018
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques.
IEEE J. Solid State Circuits, 2015
2014
A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2007
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL.
IEEE J. Solid State Circuits, 2007