Patrick Judd

Orcid: 0000-0001-8177-200X

According to our database1, Patrick Judd authored at least 24 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
FP8 Formats for Deep Learning.
CoRR, 2022

2020
Integer Quantization for Deep Learning Inference: Principles and Empirical Evaluation.
CoRR, 2020

2019
Accelerating Image-Sensor-Based Deep Learning Applications.
IEEE Micro, 2019

ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Proteus: Exploiting precision variability in deep neural networks.
Parallel Comput., 2018

Value-Based Deep-Learning Acceleration.
IEEE Micro, 2018

DPRed: Making Typical Activation Values Matter In Deep Learning Computing.
CoRR, 2018

Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How.
CoRR, 2018

Exploiting Typical Values to Accelerate Deep Learning.
Computer, 2018

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Loom: exploiting weight and activation precisions to accelerate convolutional neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks.
CoRR, 2017

Cnvlutin2: Ineffectual-Activation-and-Weight-Free Deep Neural Network Computing.
CoRR, 2017

Tartan: Accelerating Fully-Connected and Convolutional Layers in Deep Learning Networks by Exploiting Numerical Precision Variability.
CoRR, 2017

Dynamic Stripes: Exploiting the Dynamic Precision Requirements of Activation Values in Neural Networks.
CoRR, 2017

Stripes: Bit-Serial Deep Neural Network Computing.
IEEE Comput. Archit. Lett., 2017

Bit-pragmatic deep neural network computing.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Bit-Pragmatic Deep Neural Network Computing.
Proceedings of the 5th International Conference on Learning Representations, 2017

2016
Stripes: Bit-serial deep neural network computing.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks.
Proceedings of the 2016 International Conference on Supercomputing, 2016

2015
Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets.
CoRR, 2015

2014
Evaluating the memory system behavior of smartphone workloads.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014


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