Jorge Albericio
According to our database1,
Jorge Albericio
authored at least 25 papers
between 2012 and 2022.
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Bibliography
2022
IEEE Trans. Computers, 2022
2020
TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training and Inference.
CoRR, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
2018
Parallel Comput., 2018
Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
Proceedings of the 5th International Conference on Learning Representations, 2017
2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 International Conference on Supercomputing, 2016
2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014
2013
ACM Trans. Archit. Code Optim., 2013
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013
2012
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
ACM Trans. Archit. Code Optim., 2012