Natalie D. Enright Jerger

According to our database1, Natalie D. Enright Jerger authored at least 71 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs.
IEEE Trans. Computers, 2019

UBERNoC: unified buffer power-efficient router for network-on-chip.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

The What's Next Intermittent Computing Architecture.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Approximate Cache Architectures.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
Proteus: Exploiting precision variability in deep neural networks.
Parallel Comput., 2018

A high-level model for exploring multi-core architectures.
Parallel Comput., 2018

Value-Based Deep-Learning Acceleration.
IEEE Micro, 2018

Approximate Computing.
IEEE Micro, 2018

A Taxonomy of General Purpose Approximate Computing Techniques.
Embedded Systems Letters, 2018

Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms.
CoRR, 2018

Exploiting Typical Values to Accelerate Deep Learning.
IEEE Computer, 2018

The EH Model: Analytical Exploration of Energy-Harvesting Architectures.
Computer Architecture Letters, 2018

Fast and Accurate Performance Analysis of Synchronization.
Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

The EH Model: Early Design Space Exploration of Intermittent Processor Architectures.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Modular Routing Design for Chiplet-Based Systems.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
On-Chip Networks, Second Edition
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2017

2016
Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors.
IEEE Micro, 2016

The Bunker Cache for spatio-value approximation.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

The Anytime Automaton.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Efficient synthetic traffic models for large, complex SoCs.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

The runahead network-on-chip.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Hierarchical Clustering for On-Chip Networks.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015
Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs.
IEEE Trans. Computers, 2015

Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets.
CoRR, 2015

Data Criticality in Network-On-Chip Design.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Improving DVFS in NoCs with Coherence Prediction.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Doppelgänger: a cache for approximate computing.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Enabling interposer-based disintegration of multi-core processors.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014
Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs.
IEEE Trans. Parallel Distrib. Syst., 2014

DART: A Programmable Architecture for NoC Simulation on FPGAs.
IEEE Trans. Computers, 2014

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs.
IEEE Trans. Computers, 2014

Evaluating the memory system behavior of smartphone workloads.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

QuT: A low-power optical Network-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Sampling-based approaches to accelerate network-on-chip simulation.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Dodec: Random-Link, Low-Radix On-Chip Networks.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Load Value Approximation.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Wormhole: Wisely Predicting Multidimensional Branches.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Accelerating network-on-chip simulation via sampling.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

SynFull: Synthetic traffic models capturing cache coherent behaviour.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Power Modeling for Heterogeneous Processors.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Efficient and programmable ethernet switching with a NoC-enhanced FPGA.
Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014

2013
Moths: Mobile threads for on-chip networks.
ACM Trans. Embedded Comput. Syst., 2013

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip.
IJARAS, 2013

Explaining Parallel Architecture Design.
Computing in Science and Engineering, 2013

DistCL: A Framework for the Distributed Execution of OpenCL Kernels.
Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

Performance analysis of broadcasting algorithms on the Intel Single-Chip Cloud Computer.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

A dual grain hit-miss detector for large die-stacked DRAM caches.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Supporting efficient collective communication in NoCs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Systems for Very Large-Scale Computing.
IEEE Micro, 2011

DART: A programmable architecture for NoC simulation on FPGAs.
Proceedings of the NOCS 2011, 2011

DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
SigNet: Network-on-chip filtering for coarse vector directories.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
On-Chip Networks
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2009

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

SCARAB: a single cycle adaptive routing and bufferless network.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Achieving predictable performance through better memory controller placement in many-core CMPs.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Circuit-Switched Coherence.
Computer Architecture Letters, 2007

An Evaluation of Server Consolidation Workloads for Multi-Core Designs.
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

2006
Friendly fire: understanding the effects of multiprocessor prefetches.
Proceedings of the 2006 IEEE International Symposium on Performance Analysis of Systems and Software, 2006


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