Natalie D. Enright Jerger

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

BlackJack: Secure machine learning on IoT devices through hardware-based shuffling.

[BibT_eX]

[DOI]

Michal Fishkin

Ourong Lin

CoRR, 2023

The Case of Unsustainable CPU Affinity.

[BibT_eX]

[DOI]

Jiechen Zhao

Katie Lim

Thomas E. Anderson

Proceedings of the 2nd Workshop on Sustainable Computer Systems, 2023

DINAR: Enabling Distribution Agnostic Noise Injection in Machine Learning Hardware.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy, 2023

2022

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion.

[BibT_eX]

[DOI]

Amlan Ganguly

Sergi Abadal

Ishan G. Thakkar

Marc D. Riedel

Masoud Babaie

Rajeev Balasubramonian

Abu Sebastian

Sudeep Pasricha

Baris Taskin

IEEE Micro, 2022

Chapter Nine - Power-gating in NoCs.

[BibT_eX]

[DOI]

Adv. Comput., 2022

ALTOCUMULUS: Scalable Scheduling for Nanosecond-Scale Remote Procedure Calls.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Exploiting Errors for Efficiency: A Survey from Circuits to Applications.

[BibT_eX]

[DOI]

Phillip Stanley-Marbell

ACM Comput. Surv., 2021

Technical perspective: A chiplet prototype system for deep learning inference.

[BibT_eX]

[DOI]

Commun. ACM, 2021

SEEC: stochastic escape express channel.

[BibT_eX]

[DOI]

Mayank Parasar

Paul V. Gratz

Proceedings of the International Conference for High Performance Computing, 2021

Ghostwriter: A Cache Coherence Protocol for Error-Tolerant Applications.

[BibT_eX]

[DOI]

Henry Kao

Proceedings of the ICPP Workshops 2021: 50th International Conference on Parallel Processing, 2021

Pitstop: Enabling a Virtual Network Free Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020

Mocktails: Capturing the Memory Behaviour of Proprietary Mobile Architectures.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Experiences with ML-Driven Design: A NoC Case Study.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

DRAIN: Deadlock Removal for Arbitrary Irregular Networks.

[BibT_eX]

[DOI]

Mayank Parasar

Paul V. Gratz

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019

CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs.

[BibT_eX]

[DOI]

Xia Zhao

Lieven Eeckhout

IEEE Trans. Computers, 2019

UBERNoC: unified buffer power-efficient router for network-on-chip.

[BibT_eX]

[DOI]

Henry Kao

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution.

[BibT_eX]

[DOI]

Mayank Parasar

Paul V. Gratz

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers.

[BibT_eX]

[DOI]

Hadi Mardani Kamali

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

The What's Next Intermittent Computing Architecture.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Approximate Cache Architectures.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

Proteus: Exploiting precision variability in deep neural networks.

[BibT_eX]

[DOI]

Raquel Urtasun

Parallel Comput., 2018

A high-level model for exploring multi-core architectures.

[BibT_eX]

[DOI]

Parallel Comput., 2018

Value-Based Deep-Learning Acceleration.

[BibT_eX]

[DOI]

Alberto Delmas Lascorz

Sayeh Sharify

IEEE Micro, 2018

Approximate Computing.

[BibT_eX]

[DOI]

IEEE Micro, 2018

A Taxonomy of General Purpose Approximate Computing Techniques.

[BibT_eX]

[DOI]

Adrian Sampson

IEEE Embed. Syst. Lett., 2018

Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms.

[BibT_eX]

[DOI]

Phillip Stanley-Marbell

CoRR, 2018

Exploiting Typical Values to Accelerate Deep Learning.

[BibT_eX]

[DOI]

Alberto Delmas Lascorz

Sayeh Sharify

Zissis Poulos

Computer, 2018

The EH Model: Analytical Exploration of Energy-Harvesting Architectures.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Fast and Accurate Performance Analysis of Synchronization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores, 2018

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

The EH Model: Early Design Space Exploration of Intermittent Processor Architectures.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers.

[BibT_eX]

[DOI]

Hadi Mardani Kamali

Muhammad Shoaib Bin Altaf

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Modular Routing Design for Chiplet-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

On-Chip Networks, Second Edition

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01755-1, 2017

2016

Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors.

[BibT_eX]

[DOI]

IEEE Micro, 2016

The Bunker Cache for spatio-value approximation.

[BibT_eX]

[DOI]

Aamer Jaleel

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

The Anytime Automaton.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Supercomputing, 2016

Efficient synthetic traffic models for large, complex SoCs.

[BibT_eX]

[DOI]

Jieming Yin

Onur Kayiran

Matthew Poremba

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

The runahead network-on-chip.

[BibT_eX]

[DOI]

Zimo Li

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Hierarchical Clustering for On-Chip Networks.

[BibT_eX]

[DOI]

Robert Hesse

Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015

Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs.

[BibT_eX]

[DOI]

Zonglin Liu

IEEE Trans. Computers, 2015

Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets.

[BibT_eX]

[DOI]

Raquel Urtasun

CoRR, 2015

Data Criticality in Network-On-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Improving DVFS in NoCs with Coherence Prediction.

[BibT_eX]

[DOI]

Robert Hesse

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Doppelgänger: a cache for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Enabling interposer-based disintegration of multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems.

[BibT_eX]

[DOI]

Yasuko Eckert

Proceedings of the 2015 International Symposium on Memory Systems, 2015

2014

Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs.

[BibT_eX]

[DOI]

Li Shen

Nong Xiao

IEEE Trans. Parallel Distributed Syst., 2014

DART: A Programmable Architecture for NoC Simulation on FPGAs.

[BibT_eX]

[DOI]

Danyao Wang

Charles Lo

Jasmina Vasiljevic

J. Gregory Steffan

IEEE Trans. Computers, 2014

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs.

[BibT_eX]

[DOI]

Ming-che Lai

Libo Huang

IEEE Trans. Computers, 2014

Evaluating the memory system behavior of smartphone workloads.

[BibT_eX]

[DOI]

Kyros Kutulakos

Serag Gadelrab

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

QuT: A low-power optical Network-on-Chip.

[BibT_eX]

[DOI]

Parisa Khadem Hamedani

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Sampling-based approaches to accelerate network-on-chip simulation.

[BibT_eX]

[DOI]

Wenbo Dai

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Dodec: Random-Link, Low-Radix On-Chip Networks.

[BibT_eX]

[DOI]

Haofan Yang

Jyoti Tripathi

Dan Gibson

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Load Value Approximation.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

[BibT_eX]

[DOI]

Zimo Li

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Wormhole: Wisely Predicting Multidimensional Branches.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Accelerating network-on-chip simulation via sampling.

[BibT_eX]

[DOI]

Wenbo Dai

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

SynFull: Synthetic traffic models capturing cache coherent behaviour.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Power Modeling for Heterogeneous Processors.

[BibT_eX]

[DOI]

Tahir Diop

Jason Helge Anderson

Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Efficient and programmable ethernet switching with a NoC-enhanced FPGA.

[BibT_eX]

[DOI]

Andrew Bitar

Jeffrey Cassidy

Vaughn Betz

Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems, 2014

2013

Moths: Mobile threads for on-chip networks.

[BibT_eX]

[DOI]

Matthew Misler

ACM Trans. Embed. Comput. Syst., 2013

Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Parisa Khadem Hamedani

Hamid Sarbazi-Azad

Int. J. Adapt. Resilient Auton. Syst., 2013

Explaining Parallel Architecture Design.

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2013

DistCL: A Framework for the Distributed Execution of OpenCL Kernels.

[BibT_eX]

[DOI]

Tahir Diop

Steven Gurfinkel

Jason Helge Anderson

Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

Performance analysis of broadcasting algorithms on the Intel Single-Chip Cloud Computer.

[BibT_eX]

[DOI]

John Matienzo

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

A dual grain hit-miss detector for large die-stacked DRAM caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels.

[BibT_eX]

[DOI]

Robert Hesse

Jeff Nicholls

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Supporting efficient collective communication in NoCs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Systems for Very Large-Scale Computing.

[BibT_eX]

[DOI]

IEEE Micro, 2011

DART: A programmable architecture for NoC simulation on FPGAs.

[BibT_eX]

[DOI]

Danyao Wang

J. Gregory Steffan

Proceedings of the NOCS 2011, 2011

DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

SigNet: Network-on-chip filtering for coarse vector directories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

On-Chip Networks

[BibT_eX]

[DOI]

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01725-4, 2009

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives.

[BibT_eX]

[DOI]

Radu Marculescu

Ümit Y. Ogras

Yatin Vasant Hoskote

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

SCARAB: a single cycle adaptive routing and bufferless network.

[BibT_eX]

[DOI]

Mitchell Hayenga

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Achieving predictable performance through better memory controller placement in many-core CMPs.

[BibT_eX]

[DOI]

Dennis Abts

John Kim

Dan Gibson

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support.

[BibT_eX]

[DOI]

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

Circuit-Switched Coherence.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2007

An Evaluation of Server Consolidation Workloads for Multi-Core Designs.

[BibT_eX]

[DOI]

Dana Vantrease

Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007

2006

Friendly fire: understanding the effects of multiprocessor prefetches.

[BibT_eX]

[DOI]

Eric L. Hill