Zissis Poulos

According to our database, Zissis Poulos authored at least 30 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

A Robust Quantile Huber Loss With Interpretable Parameter Adjustment In Distributional Reinforcement Learning.

Parvin Malekzadeh, Konstantinos N. Plataniotis, Zissis Poulos, Zeyu Wang

CoRR, 2024

2023

Gamma and vega hedging using deep distributional reinforcement learning.

Jay Cao, Jacky Chen, Soroush Farghadani, John Hull, Zissis Poulos, Zeyu Wang, Jun Yuan

Frontiers Artif. Intell., February, 2023

2021

Deep Hedging of Derivatives Using Reinforcement Learning.

Jay Cao, Jacky Chen, John Hull, Zissis Poulos

CoRR, 2021

Valuing Exotic Options and Estimating Model Risk.

Jay Cao, Jacky Chen, John Hull, Zissis Poulos

CoRR, 2021

2020

On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle.

Keerthi Nelaturu, John Adler, Marco Merlini, Ryan Berryhill, Neil Veira, Zissis Poulos, Andreas G. Veneris

IEEE Trans. Engineering Management, 2020

Searching for Bugs Using Probabilistic Suspect Implications.

Neil Veira, Zissis Poulos, Andreas G. Veneris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Accelerating Image-Sensor-Based Deep Learning Applications.

Mostafa Mahmoud, Dylan Malone Stuart, Zissis Poulos, Alberto Delmas Lascorz, Patrick Judd, Sayeh Sharify, Milos Nikolic, Kevin Siu, Isak Edo Vivancos, Jorge Albericio, Andreas Moshovos

IEEE Micro, 2019

Training CNNs faster with Dynamic Input and Kernel Downsampling.

Zissis Poulos, Ali Nouri, Andreas Moshovos

CoRR, 2019

ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning.

Alberto Delmas Lascorz, Sayeh Sharify, Isak Edo Vivancos, Dylan Malone Stuart, Omar Mohamed Awad, Patrick Judd, Mostafa Mahmoud, Milos Nikolic, Kevin Siu, Zissis Poulos, Andreas Moshovos

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Laconic deep learning inference acceleration.

Sayeh Sharify, Alberto Delmas Lascorz, Mostafa Mahmoud, Milos Nikolic, Kevin Siu, Dylan Malone Stuart, Zissis Poulos, Andreas Moshovos

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Deep Learning Language Modeling Workloads: Where Time Goes on Graphics Processors.

Ali Hadi Zadeh, Zissis Poulos, Andreas Moshovos

Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks.

Alberto Delmas Lascorz, Patrick Judd, Dylan Malone Stuart, Zissis Poulos, Mostafa Mahmoud, Sayeh Sharify, Milos Nikolic, Kevin Siu, Andreas Moshovos

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Suspect2vec: a suspect prediction model for directed RTL debugging.

Neil Veira, Zissis Poulos, Andreas G. Veneris

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Failure Triage in RTL Regression Verification.

Zissis Poulos, Andreas G. Veneris

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How.

Alberto Delmas, Patrick Judd, Dylan Malone Stuart, Zissis Poulos, Mostafa Mahmoud, Sayeh Sharify, Milos Nikolic, Andreas Moshovos

CoRR, 2018

Exploiting Typical Values to Accelerate Deep Learning.

Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas Lascorz, Sayeh Sharify, Zissis Poulos, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger

Computer, 2018

Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning.

Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas, Sayeh Sharify, Mostafa Mahmoud, Tayler H. Hetherington, Milos Nikolic, Dylan Malone Stuart, Kevin Siu, Zissis Poulos, Tor M. Aamodt, Natalie D. Enright Jerger

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Astraea: A Decentralized Blockchain Oracle.

John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania

Proceedings of the IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, 2018

Suspect set prediction in RTL bug hunting.

Neil Veira, Zissis Poulos, Andreas G. Veneris

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Learning lemma support graphs in Quip and IC3.

Ryan Berryhill, Neil Veira, Andreas G. Veneris, Zissis Poulos

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism.

Koushik Pal, Zissis Poulos, Edward Kim, Andreas G. Veneris

Proceedings of the Advances in Data Mining. Applications and Theoretical Aspects, 2017

2016

Exemplar-based Failure Triage for Regression Design Debugging.

Zissis Poulos, Andreas G. Veneris

J. Electron. Test., 2016

On simulation-based metrics that characterize the behavior of RTL errors.

Zissis Poulos, Ryan Berryhill, John Adler, Andreas G. Veneris

Proceedings of the Summer Computer Simulation Conference, 2016

2015

Mining simulation metrics for failure triage in regression testing.

Zissis Poulos, Andreas G. Veneris

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Clustering-based revision debug in regression verification.

Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Clustering-based failure triage for RTL regression debugging.

Zissis Poulos, Andreas G. Veneris

Proceedings of the 2014 International Test Conference, 2014

Simulation and satisfiability guided counter-example triage for RTL design debugging.

Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

A failure triage engine based on error trace signature extraction.

Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Accelerating post silicon debug of deep electrical faults.

Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Leveraging reconfigurability to raise productivity in FPGA functional debug.

Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012