Paul Lane

According to our database1, Paul Lane authored at least 1 paper in 2010.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010


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