Mark Jacunski

According to our database, Mark Jacunski authored at least 4 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.

Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2011

Embedded DRAM in 45-nm Technology and Beyond.

Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli

IEEE Des. Test Comput., 2011

2010

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.

Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.

Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007